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參數(shù)資料
| 型號： | XR-T7295 |
| 廠商： | Exar Corporation |
| 英文描述： | DS3/Sonet STS-1 Integrated Line Receiver |
| 中文描述： | DS3/Sonet STS - 1的集成線路接收器 |
| 文件頁數(shù)： | 14/20頁 |
| 文件大小： | 226K |
| 代理商： | XR-T7295 |
XR-T7295
14
Rev. 1.05
TIMING CHARACTERISTICS
Test Conditions: All Timing Characteristics are Measrured with 10pF Loading, -40
°
C
5V
10%
T
A
+85
°
C, V
DD
=
Symbol
Parameter
Min
Typ
Max
Unit
tRCH1RCH2
Clock Rise Time (10% - 90%)
3.5
ns
tRCL2RCL1
Clock Fall Time (10% - 90%)
2.5
ns
tRDVRCL
Receive Data Set-up Time
5.0
ns
tRCLRDX
Receive Data Hold Time
Receive Propagation Delay
1
8.5
ns
tRCHRDV
0.6
3.7
ns
Clock Duty Cycle
45
50
55
%
Note
s
1
The total delay from R
IN
to the digital outputs RPDATA and RNDATA is three and a half RCLK clocks.
Table 8. System Interface Timing Characteristics
Figure 11. Timing Diagram for System Interface
RCLK
(RC)
RPDATA
OR
RNDATA
(RD)
tRCHRDV
tRCL2RCL1
tRCH1RCH2
tRCLRDX
tRDVRCL
BOARD LAYOUT CONSIDERATIONS
Power Supply Bypassing
Figure 12illustrates the recommended power supply
bypassing network. A 0.1
μ
F capacitor bypasses the
digital supplies. The analog supply V
DD
A is bypassed by
using a 0.1
μ
F capacitor and a shield bead that removes
significant amounts of high-frequency noise generated by
the system and by the device logic. Good quality,
high-frequency (low lead inductance) capacitors should
be used. Finally, it is most important that all ground
connections be made to a low-impedance ground plane.
Receive Input
The connections to the receive input pin, R
IN
, must be
carefully considered. Noise-coupling must be minimized
along the path from the signal entering the board to the
input pin. Any noise coupled into the XR-T7295 input
directly degrades the signal-to-noise ratio of the input
signal and may degrade sensitivity.
PLL Filter Capacitor
The PLL filter capacitor between pins LPF1 and LPF2
must be placed as close to the chip as possible. The LPF1
and LPF2 pins are adjacent, allowing for short lead
lengths with no crossovers to the external capacitor.
Noise-coupling into the LPF1 and LPF2 pins may
degrade PLL performance.
Handling Precautions
Although protection circuitry has been designed into this
device, proper precautions should be taken to avoid
exposure to electrostatic discharge (ESD) during
handling and mounting.
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