- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300162 > XQ4013E-4PG223M (XILINX INC) Field Programmable Gate Array (FPGA) PDF資料下載
參數(shù)資料
| 型號： | XQ4013E-4PG223M |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封裝： | CERAMIC, PGA-223 |
| 文件頁數(shù)： | 5/36頁 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
第1頁第2頁第3頁第4頁當前第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
QPRO XQ4000E/EX QML High-Reliability FPGAs
DS021 (v2.2) June 25, 2000
2-55
Product Specification
1-800-255-7778
R
1
2
3
4
5
6
XQ4000E Guaranteed Input and Output Parameters (Pin-to-Pin, TTL I/O)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Pin-to-pin timing parameters are
derived from measuring external and internal test patterns
and are guaranteed over worst-case operating conditions
(supply voltage and junction temperature). Listed below are
representative values for typical pin locations and normal
clock loading. For more specific, more precise, and
worst-case guaranteed data, reflecting the actual routing
structure, use the values provided by the static timing ana-
lyzer (TRCE in the Xilinx Development System) and
back-annotated to the simulation netlist. These path delays,
provided as a guideline, have been extracted from the static
timing analyzer report. Values apply to all XQ4000E devices
unless otherwise noted.
Symbol
Description
Device
-3
-4
Units
TICKOF
(Max)
Global clock to output (fast) using OFF
XQ4005E
-
14.0
ns
XQ4010E
10.9
16.0
ns
XQ4013E
11.0
16.5
ns
XQ4025E
-
17.0
ns
TICKO
(Max)
Global clock to output (slew-limited) using OFF
XQ4005E
-
18.0
ns
XQ4010E
14.9
20.0
ns
XQ4013E
15.0
20.5
ns
XQ4025E
-
21.0
ns
TPSUF
(Min)
Input setup time, using IFF (no delay)
XQ4005E
-
2.0
ns
XQ4010E
0.2
1.0
ns
XQ4013E
0
0.5
ns
XQ4025E
-
0
ns
TPHF
(Min)
Input hold time, using IFF (no delay)
XQ4005E
-
4.6
ns
XQ4010E
5.5
6.0
ns
XQ4013E
6.5
7.0
ns
XQ4025E
-
8.0
ns
TPSU
(Min)
Input setup time, using IFF (with delay)
XQ4005E
-
8.5
ns
XQ4010E
7.0
8.5
ns
XQ4013E
7.0
8.5
ns
XQ4025E
-
9.5
ns
TPH
(Min)
Input hold time, using IFF (with delay)
XQ4005E
-
0
ns
XQ4010E
0
ns
XQ4013E
0
ns
XQ4025E
-
0
ns
Notes:
1.
OFF = Output Flip-Flop
2.
IFF = Input Flip-Flop or Latch
OFF
TPG
Global Clock-to-Output Delay
DS021_04_060100
OFF
TPG
Global Clock-to-Output Delay
DS021_04_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
IFF
TPG
D
Input
Setup
and Hold
Time
DS021_05_060100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XR16M770IL24 | 1 CHANNEL(S), 16M bps, SERIAL COMM CONTROLLER, QCC24 |
| XR16M780IM48 | SERIAL COMM CONTROLLER, PQFP48 |
| XR68C681CJ | XR-68C681CJ PLCC 44 UART 2 CHANELS |
| XS170 | Multifunction Telecom Switch |
| XS170S | Multifunction Telecom Switch |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4013EX-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3BG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3BG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復。