- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄300162 > XQ4013E-4PG223M (XILINX INC) Field Programmable Gate Array (FPGA) PDF資料下載
參數(shù)資料
| 型號： | XQ4013E-4PG223M |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Field Programmable Gate Array (FPGA) |
| 中文描述： | FPGA, 576 CLBS, 10000 GATES, 111 MHz, CPGA223 |
| 封裝： | CERAMIC, PGA-223 |
| 文件頁數(shù)： | 24/36頁 |
| 文件大小： | 294K |
| 代理商： | XQ4013E-4PG223M |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁當前第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
QPRO XQ4000E/EX QML High-Reliability FPGAs
2-72
DS021 (v2.2) June 25, 2000
1-800-255-7778
Product Specification
R
XQ4028EX IOB Input Switching Characteristic Guidelines (Continued)
Symbol
Description
-4
Units
Min
Setup Times
TPICK
Pad to Clock (IK), no delay
2.5
ns
TPICKP
Pad to Clock (IK), partial delay
10.8
ns
TPICKD
Pad to Clock (IK), full delay
15.7
ns
TPICKF
Pad to Clock (IK), via transparent Fast Capture Latch, no delay
3.9
ns
TPICKFP
Pad to Clock (IK), via transparent Fast Capture Latch, partial delay
12.3
ns
TPOCK
Pad to Fast Capture Latch Enable (OK), no delay
0.8
ns
TPOCKP
Pad to Fast Capture Latch Enable (OK), partial delay
9.1
ns
Setup Times (TTL or CMOS Inputs)
TECIK
Clock Enable (EC) to Clock (IK)
0.3
ns
Hold Times
TIKPI
Pad to Clock (IK), no delay
0
ns
TIKPIP
Pad to Clock (IK), partial delay
0
ns
TIKPID
Pad to Clock (IK), full delay
0
ns
TIKPIF
Pad to Clock (IK) via transparent Fast Capture Latch, no delay
0
ns
TIKFPIP
Pad to Clock (IK) via transparent Fast Capture Latch, partial delay
0
ns
TIKFPID
Pad to Clock (IK) via transparent Fast Capture Latch, full delay
0
ns
TIKEC
Clock Enable (EC) to Clock (IK), no delay
0
ns
TIKECP
Clock Enable (EC) to Clock (IK), partial delay
0
ns
TIKECD
Clock Enable (EC) to Clock (IK), full delay
0
ns
TOKPI
Pad to Fast Capture Latch Enable (OK), no delay
0
ns
TOKPIP
Pad to Fast Capture Latch Enable (OK), partial delay
0
ns
Notes:
1.
For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 70.
2.
For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on page 70.
相關PDF資料 |
PDF描述 |
|---|---|
| XR16M770IL24 | 1 CHANNEL(S), 16M bps, SERIAL COMM CONTROLLER, QCC24 |
| XR16M780IM48 | SERIAL COMM CONTROLLER, PQFP48 |
| XR68C681CJ | XR-68C681CJ PLCC 44 UART 2 CHANELS |
| XS170 | Multifunction Telecom Switch |
| XS170S | Multifunction Telecom Switch |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XQ4013EX-3BG191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3BG191N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3BG196M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3BG196N | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
| XQ4013EX-3CB191M | 制造商:XILINX 制造商全稱:XILINX 功能描述:QML High-Reliability FPGAs |
發(fā)布緊急采購，3分鐘左右您將得到回復。