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QPRO XQ4000XL Series QML High-Reliability FPGAs
DS029 (v1.3) June 25, 2000
Product Specification
www.xilinx.com
1-800-255-7778
7
R
Hold Time After Clock K
T
CKI
T
CKIH
T
CKHH0
T
CKHH1
T
CKHH2
T
CKDI
T
CKEC
T
CKR
Clock
T
CH
T
CL
Set/Reset Direct
T
RPW
T
RIO
Global Set/Reset
T
MRW
T
MRQ
F
TOG
F/G inputs
F/G inputs via H
C inputs via SR/H0 through H
C inputs via H1 through H
C inputs via D
IN
/H2 through H
C inputs via D
IN
/H2
C inputs via EC
C inputs via SR, going Low (inactive)
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
Clock High time
Clock Low time
3.0
3.0
-
-
2.5
2.5
-
-
ns
ns
Width (High)
Delay from C inputs via S/R, going High to Q
3.0
-
-
2.5
-
-
ns
ns
3.7
2.8
Minimum GSR pulse width
Delay from GSR input to any Q
Toggle frequency (MHz) (for export control)
-
19.8
-
15.0
ns
See
page 17
for T
RRI
values per device.
-
166
-
200
MHz
CLB Switching Characteristics
(Continued)
Symbol
Description
-3
-1
Units
Min
Max
Min
Max
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