參數(shù)資料
型號(hào)： XQ4000XL
廠(chǎng)商： Xilinx, Inc.
英文描述： QML High-Reliability FPGAs
中文描述： QML第高可靠性的FPGA
文件頁(yè)數(shù)： 14/22頁(yè)
文件大?。?/td> 162K
代理商： XQ4000XL
QPRO XQ4000XL Series QML High-Reliability FPGAs
14
www.xilinx.com
1-800-255-7778
DS029 (v1.3) June 25, 2000
Product Specification
R
Global Early Clock BUFEs 1, 2, 5, and 6 Setup and Hold for IFF and FCL
(1,2)
Symbol
Description
Device
-3
-1
Min
Min
No Delay
T
PSEN
/T
PHEN
T
PFSEN
/T
PFHEN
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQ4013XL
1.2 / 4.7
-
XQ4036XL
1.2 / 6.7
-
XQ4062XL
1.2 / 8.4
-
XQ4085XL
-
0.9 / 6.6
Partial Delay
T
PSEPN
/T
PHEP
T
PFSEP
/T
PFHEP
Global early clock and IFF
(3)
Global early clock and FCL
(4)
XQ4013XL
6.4 / 0.0
-
XQ4036XL
7.0 / 0.8
-
XQ4062XL
9.0 / 0.8
-
XQ4085XL
-
11.0 / 0.0
Full Delay
T
PSEPD
/T
PHED
Global early clock and IFF
(3)
XQ4013XL
12.0 / 0.0
-
XQ4036XL
13.8 / 0.0
-
XQ4062XL
13.1 / 0.0
-
XQ4085XL
-
13.6 / 0.0
Notes:
1.
2.
The XQ4013XL, XQ4036XL, and XQ4062XL have significantly faster partial and full delay setup times than other devices.
Input setup time is measured with the fastest route and the lightest load. Input hold time is measured using the furthest distance and
a reference load of one clock pin per IOB as well as driving all accessible CLB flip-flops. For designs with a smaller number of clock
loads, the pad-to-IOB clock pin delay as determined by the static timing analyzer (TRCE) can be used as a worst-case pin-to-pin
no-delay input hold specification.
IFF = Input Flip-Flop or Latch
FCL = Fast Capture Latch
3.
4.
相關(guān)PDF資料
PDF描述
XQ4013XL-1BG228M QML High-Reliability FPGAs
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