參數(shù)資料
型號: XPC850DECVR66BU
廠商: Freescale Semiconductor
文件頁數(shù): 52/72頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC 66MHZ 256-PBGA
標(biāo)準(zhǔn)包裝: 60
系列: MPC8xx
處理器類型: 32-位 MPC8xx PowerQUICC
速度: 66MHz
電壓: 3.3V
安裝類型: 表面貼裝
封裝/外殼: 256-LBGA
供應(yīng)商設(shè)備封裝: 256-PBGA(23x23)
包裝: 托盤
MPC850 PowerQUICC Integrated Communications Processor Hardware Specifications, Rev. 2
56
Freescale Semiconductor
CPM Electrical Characteristics
Figure 55. Ethernet Transmit Timing Diagram
8.8
SMC Transparent AC Electrical Specifications
Figure 21 provides the SMC transparent timings as shown in Figure 56.
Table 21. Serial Management Controller Timing
Num
Characteristic
All Frequencies
Unit
Min
Max
150
SMCLKx clock period 1
1
The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.
100.00
ns
151
SMCLKx width low
50.00
ns
151a
SMCLKx width high
50.00
ns
152
SMCLKx rise/fall time
15.00
ns
153
SMTXDx active delay (from SMCLKx falling edge)
10.00
50.00
ns
154
SMRXDx/SMSYNx setup time
20.00
ns
155
SMRXDx/SMSYNx hold time
5.00
ns
TCLKx
128
TxDx
(Output)
128
TENA(RTSx)
(Input)
NOTES:
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
1.
2.
RENA(CDx)
(Input)
133
134
132
131
130
129
(NOTE 2)
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