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| 型號(hào)： | XCV812E-7BG560C |
| 廠商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 92/118頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 560-MBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E EM |
| LAB/CLB數(shù)： | 4704 |
| 邏輯元件/單元數(shù)： | 21168 |
| RAM 位總計(jì)： | 1146880 |
| 輸入/輸出數(shù)： | 404 |
| 門(mén)數(shù)： | 254016 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 560-LBGA，金屬 |
| 供應(yīng)商設(shè)備封裝： | 560-MBGA（42.5x42.5） |
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Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v3.0) March 21, 2014
Module 3 of 4
19
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
Revision History
The following table shows the revision history for this document.
CLKDLLHF
CLKDLL
Units
Description
Symbol
F
CLKIN
Min
Max
Min
Max
Input Clock Period Tolerance
TIPTOL
-1.0
-
1.0
ns
Input Clock Jitter Tolerance (Cycle to Cycle)
TIJITCC
-
± 150
-
± 300
ps
Time Required for DLL to Acquire Lock(6)
TLOCK
> 60 MHz
-
20
-
20
μs
50 - 60 MHz
-
25
μs
40 - 50 MHz
-
50
μs
30 - 40 MHz
-
90
μs
25 - 30 MHz
-
120
μs
Output Jitter (cycle-to-cycle) for any DLL Clock Output(1)
TOJITCC
± 60
ps
Phase Offset between CLKIN and CLKO(2)
TPHIO
± 100
ps
Phase Offset between Clock Outputs on the DLL(3)
TPHOO
± 140
ps
Maximum Phase Difference between CLKIN and CLKO(4)
TPHIOM
± 160
ps
Maximum Phase Difference between Clock Outputs on the DLL(5)
TPHOOM
± 200
ps
Notes:
1.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding
input clock jitter.
2.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5.
Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6.
Add 30% to the value for Industrial grade parts.
Date
Version
Revision
03/23/2000
1.0
Initial Xilinx release.
08/01/2000
1.1
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
09/19/2000
1.2
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV812E-7BG560I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG676I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV812E-7BG900I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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