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| 型號(hào)： | XCV600E-8FG676C |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 223/233頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 676-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 3456 |
| 邏輯元件/單元數(shù)： | 15552 |
| RAM 位總計(jì)： | 294912 |
| 輸入/輸出數(shù)： | 444 |
| 門(mén)數(shù)： | 985882 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 676-BGA |
| 供應(yīng)商設(shè)備封裝： | 676-FBGA（27x27） |
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
DS022-2 (v3.0) March 21, 2014
Module 2 of 4
Production Product Specification
3
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
Eight I/O banks result from separating each edge of the
FPGA into two banks, as shown in Figure 3. Each bank has
multiple VCCO pins, all of which must be connected to the
same voltage. This voltage is determined by the output
standards in use.
Within a bank, output standards can be mixed only if they
use the same VCCO. Compatible standards are shown in
Table 2. GTL and GTL+ appear under all voltages because
their open-drain outputs do not depend on VCCO.
Some input standards require a user-supplied threshold
voltage, VREF. In this case, certain user-I/O pins are auto-
matically configured as inputs for the VREF voltage. Approx-
imately one in six of the I/O pins in the bank assume this
role.
The VREF pins within a bank are interconnected internally
and consequently only one VREF voltage can be used within
each bank. All VREF pins in the bank, however, must be con-
nected to the external voltage source for correct operation.
Within a bank, inputs that require VREF can be mixed with
those that do not. However, only one VREF voltage can be
used within a bank.
In
Virtex-E,
input
buffers
with
LVTTL,
LVCMOS2,
LVCMOS18, PCI33_3, PCI66_3 standards are supplied by
VCCO rather than VCCINT. For these standards, only input
and output buffers that have the same VCCO can be mixed
together.
The VCCO and VREF pins for each bank appear in the device
pin-out tables and diagrams. The diagrams also show the
bank affiliation of each I/O.
Within a given package, the number of VREF and VCCO pins
can vary depending on the size of device. In larger devices,
more I/O pins convert to VREF pins. Since these are always
a super set of the VREF pins used for smaller devices, it is
possible to design a PCB that permits migration to a larger
device if necessary. All the VREF pins for the largest device
anticipated must be connected to the VREF voltage, and not
used for I/O.
In smaller devices, some VCCO pins used in larger devices
do not connect within the package. These unconnected pins
can be left unconnected externally, or can be connected to
the VCCO voltage to permit migration to a larger device if
necessary.
Configurable Logic Blocks
The basic building block of the Virtex-E CLB is the logic cell
(LC). An LC includes a 4-input function generator, carry
logic, and a storage element. The output from the function
generator in each LC drives both the CLB output and the D
input of the flip-flop. Each Virtex-E CLB contains four LCs,
organized in two similar slices, as shown in Figure 4.
Figure 5 shows a more detailed view of a single slice.
In addition to the four basic LCs, the Virtex-E CLB contains
logic that combines function generators to provide functions
of five or six inputs. Consequently, when estimating the
number of system gates provided by a given device, each
CLB counts as 4.5 LCs.
Look-Up Tables
Virtex-E function generators are implemented as 4-input
look-up tables (LUTs). In addition to operating as a function
generator, each LUT can provide a 16 x 1-bit synchronous
RAM. Furthermore, the two LUTs within a slice can be com-
bined to create a 16 x 2-bit or 32 x 1-bit synchronous RAM,
or a 16 x 1-bit dual-port synchronous RAM.
The Virtex-E LUT can also provide a 16-bit shift register that
is ideal for capturing high-speed or burst-mode data. This
mode can also be used to store data in applications such as
Digital Signal Processing.
Figure 3: Virtex-E I/O Banks
Table 2: Compatible Output Standards
VCCO
Compatible Standards
3.3 V
PCI, LVTTL, SSTL3 I, SSTL3 II, CTT, AGP, GTL,
GTL+, LVPECL
2.5 V
SSTL2 I, SSTL2 II, LVCMOS2, GTL, GTL+,
BLVDS, LVDS
1.8 V
LVCMOS18, GTL, GTL+
1.5 V
HSTL I, HSTL III, HSTL IV, GTL, GTL+
ds022_03_121799
Bank 0
GCLK3 GCLK2
GCLK1 GCLK0
Bank 1
Bank 5
Bank 4
VirtexE
Device
Bank
7
Bank
6
Bank
2
Bank
3
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|---|---|
| XCV600E-8FG676I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV600E-8FG680C | 功能描述:IC FPGA 1.8V C-TEMP 680-FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV600E8FG680C-0773 | 制造商:Xilinx 功能描述: |
| XCV600E-8FG680I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV600E-8FG900C | 功能描述:IC FPGA 1.8V C-TEMP 900-FBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
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