參數(shù)資料
型號(hào)： XCV405E-6FG676I
廠商： XILINX INC
元件分類： FPGA
英文描述： Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
中文描述： FPGA, 2400 CLBS, 129600 GATES, 357 MHz, PBGA676
封裝： PLASTIC, FBGA-676
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 191K
代理商： XCV405E-6FG676I
Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.3.2) March 14, 2003
Module 3 of 4
1-800-255-7778
17
R
Virtex-E Pin-to-Pin Input Parameter Guidelines
All devices are 100% functionally tested. Listed below are representative values for typical pin locations and normal clock
loading. Values are expressed in nanoseconds unless otherwise noted.
Global Clock Set-Up and Hold for LVTTL Standard, with DLL
Global Clock Set-Up and Hold for LVTTL Standard, without DLL
Description(1)
Symbol
Device(3)
Speed Grade(2)
Units
Min
-8-7-6
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time
delay by the values shown in ‘‘IOB Input Switching
No Delay
TPSDLL/TPHDLL
XCV405E
1.5 / –0.4
1.6 / –0.4
1.7 / –0.4
ns
Global Clock and IFF, with DLL
XCV812E
1.5 / –0.4
1.6 / –0.4
1.7 / –0.4
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
DLL output jitter is already included in the timing calculation.
Description(1)
Symbol
Device(3)
Speed Grade(2)
Units
Min
-8
-7
-6
Input Setup and Hold Time Relative to Global Clock Input Signal
for LVTTL Standard.
For data input with different standards, adjust the setup time delay
Full Delay
TPSFD/TPHFD
XCV405E
2.3 / 0
ns
Global Clock and IFF, without DLL
XCV812E
2.5 / 0
ns
Notes:
1.
IFF = Input Flip-Flop or Latch
2.
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured
relative to the Global Clock input signal with the slowest route and heaviest load.
3.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values can not be guaranteed “best-case”, but
if a “0” is listed, there is no positive hold time.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCV405E-6FG900C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-6FG900I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-7BG404C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-7BG404I 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
XCV405E-7BG556C 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays
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