參數(shù)資料
型號: XCV405E-6FG676C
英文描述: FPGA
中文描述: FPGA的
文件頁數(shù): 3/20頁
文件大小: 242K
代理商: XCV405E-6FG676C
Virtex
-E 1.8 V Extended Memory Field Programmable Gate Arrays
DS025-3 (v2.1) February 1, 2002
1-800-255-7778
Module 3 of 4
3
R
DC Input and Output Levels
Values for V
IL
and V
IH
are recommended input voltages. Values for I
OL
and I
OH
are guaranteed over the recommended
operating conditions at the V
OL
and V
OH
test points. Only selected standards are tested. These are chosen to ensure that
all standards meet their specifications. The selected standards are tested at minimum V
CCO
with the respective V
OL
and
V
OH
voltage levels shown. Other standards are sample tested.
Input/Output
Standard
V
IL
V
IH
V
OL
V
OH
I
OL
I
OH
V, min
V, max
V, min
V, max
V, Max
V, Min
mA
mA
LVTTL
(1)
0.5
0.8
2.0
3.6
0.4
2.4
24
24
LVCMOS2
0.5
0.7
1.7
2.7
0.4
1.9
12
12
LVCMOS18
0.5
20% V
CCO
70% V
CCO
1.95
0.4
V
CCO
0.4
8
8
PCI, 3.3 V
0.5
30% V
CCO
50% V
CCO
V
CCO
+ 0.5
10% V
CCO
90% V
CCO
Note 2
Note 2
GTL
0.5
V
REF
0.05
V
REF
+ 0.05
3.6
0.4
n/a
40
n/a
GTL+
0.5
V
REF
0.1
V
REF
+ 0.1
3.6
0.6
n/a
36
n/a
HSTL I
(3)
0.5
V
REF
0.1
V
REF
+ 0.1
3.6
0.4
V
CCO
0.4
8
8
HSTL III
0.5
V
REF
0.1
V
REF
+ 0.1
3.6
0.4
V
CCO
0.4
24
8
HSTL IV
0.5
V
REF
0.1
V
REF
+ 0.1
3.6
0.4
V
CCO
0.4
48
8
SSTL3 I
0.5
V
REF
0.2
V
REF
+ 0.2
3.6
V
REF
0.6
V
REF
+ 0.6
8
8
SSTL3 II
0.5
V
REF
0.2
V
REF
+ 0.2
3.6
V
REF
0.8
V
REF
+ 0.8
16
16
SSTL2 I
0.5
V
REF
0.2
V
REF
+ 0.2
3.6
V
REF
0.61
V
REF
+ 0.61
7.6
7.6
SSTL2 II
0.5
V
REF
0.2
V
REF
+ 0.2
3.6
V
REF
0.80
V
REF
+ 0.80
15.2
15.2
CTT
0.5
V
REF
0.2
V
REF
+ 0.2
3.6
V
REF
0.4
V
REF
+ 0.4
8
8
AGP
0.5
V
REF
0.2
V
REF
+ 0.2
3.6
10% V
CCO
90% V
CCO
Note 2
Note 2
Notes:
1.
2.
3.
V
OL
and V
OH
for lower drive currents are sample tested.
Tested according to the relevant specifications.
DC input and output levels for HSTL18 (HSTL I/O standard with V
CCO
of 1.8 V) are provided in an
HSTL white paper
on the Xilinx
website.
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