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參數(shù)資料
| 型號： | XCV405E-6FG676C |
| 英文描述： | FPGA |
| 中文描述： | FPGA的 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 242K |
| 代理商： | XCV405E-6FG676C |
Recommended Operating Conditions
DC Characteristics Over Recommended Operating Conditions
Power-On Power Supply Requirements
Xilinx FPGAs require a certain amount of supply current during power-on to insure proper device operation. The actual
current consumed depends on the power-on ramp rate of the power supply. This is the time required to reach the nominal
power supply voltage of the device
1
from 0 V. The fastest suggested ramp rate is 0 V to nominal voltage in 2 ms and the
slowest allowed ramp rate is 0 V to nominal voltage in 50 ms.
Symbol
Description
Min
Max
Units
V
CCINT
Internal Supply voltage relative to GND, T
J
= 0
°
C to +85
°
C
Internal Supply voltage relative to GND, T
J
=
–
40
°
C to +100
°
C
Supply voltage relative to GND, T
J
= 0
°
C to +85
°
C
Supply voltage relative to GND, T
J
=
–
40
°
C to +100
°
C
Input signal transition time
Commercial
1.8
–
5%
1.8 + 5%
V
Industrial
1.8
–
5%
1.8 + 5%
V
V
CCO
Commercial
1.2
3.6
V
Industrial
1.2
3.6
V
T
IN
250
ns
Symbol
Description
1
Device
Min
Max
Units
V
DRINT
Data Retention V
CCINT
Voltage
(below which configuration data might be lost)
All
1.5
V
V
DRIO
Data Retention V
CCO
Voltage
(below which configuration data might be lost)
All
1.2
V
I
CCINTQ
Quiescent V
CCINT
supply current
1
XCV405E
400
mA
XCV812E
500
mA
I
CCOQ
Quiescent V
CCO
supply current
1
XCV405E
2
mA
XCV812E
2
mA
I
L
Input or output leakage current
All
–
10
+10
m
A
C
IN
I
RPU
I
RPD
Input capacitance (sample tested)
BGA, PQ, HQ, packages
All
8
pF
Pad pull-up (when selected) @ V
in
= 0 V, V
CCO
= 3.3 V (sample tested)
Pad pull-down (when selected) @ V
in
= 3.6 V (sample tested)
All
Note 2
0.25
mA
Note 2
0.25
mA
Notes:
1.
2.
With no output current loads, no active input pull-up resistors, all I/O pins 3-stated and floating.
Internal pull-up and pull-down resistors guarantee valid logic levels at unconnected input pins. These pull-up and pull-down resistors
do not guarantee valid logic levels when input pins are connected to other circuits.
Product (Commercial Grade)
Description
2
Current Requirement
3
XCV50E - XCV600E
Minimum required current supply
500 mA
XCV812E - XCV2000E
Minimum required current supply
1 A
XCV2600E - XCV3200E
Minimum required current supply
1.2 A
Virtex-E Family, Industrial Grade
Minimum required current supply
2 A
Notes:
1.
Ramp rate used for this specification is from 0 - 1.8 V DC. Peak current occurs on or near the internal power-on reset threshold and
lasts for less than 3 ms.
Devices are guaranteed to initialize properly with the minimum current available from the power supply as noted above.
Larger currents might result if ramp rates are forced to be faster.
2.
3.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| XCV405E-6FG676I | 功能描述:IC FPGA 1.8V 676-BGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E EM 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標準包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計:4866048 輸入/輸出數(shù):480 門數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應商設備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV405E-6FG900C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-6FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
| XCV405E-7BG404I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Extended Memory Field Programmable Gate Arrays |
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