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參數(shù)資料
| 型號： | XCV200-6BGG256I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1176 CLBS, 236666 GATES, 333 MHz, PBGA256 |
| 封裝： | BGA-256 |
| 文件頁數(shù)： | 14/24頁 |
| 文件大小： | 167K |
| 代理商： | XCV200-6BGG256I |
Virtex 2.5 V Field Programmable Gate Arrays
R
DS003-3 (v3.2) September 10, 2002
Module 3 of 4
Production Product Specification
1-800-255-7778
21
DLL Timing Parameters
All devices are 100 percent functionally tested. Because of the difficulty in directly measuring many internal timing
parameters, those parameters are derived from benchmark timing patterns. The following guidelines reflect worst-case
values across the recommended operating conditions.
DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
Description
Symbol
Speed Grade
Units
-6
-5
-4
Min
Max
Min
Max
Min
Max
Input Clock Frequency (CLKDLLHF)
FCLKINHF
60
200
60
180
60
180
MHz
Input Clock Frequency (CLKDLL)
FCLKINLF
25
100
25
90
25
90
MHz
Input Clock Pulse Width (CLKDLLHF)
TDLLPWHF
2.0
-
2.4
-
2.4
-
ns
Input Clock Pulse Width (CLKDLL)
TDLLPWLF
2.5
-
3.0
-
ns
Notes:
1.
All specifications correspond to Commercial Operating Temperatures (0°C to + 85°C).
Description
Symbol
F
CLKIN
CLKDLLHF
CLKDLL
Units
Min
Max
Min
Max
Input Clock Period Tolerance
TIPTOL
-
1.0
-
1.0
ns
Input Clock Jitter Tolerance (Cycle to Cycle)
TIJITCC
-
± 150
-
± 300
ps
Time Required for DLL to Acquire Lock
TLOCK
> 60 MHz
-
20
-
20
s
50 - 60 MHz
-
25
s
40 - 50 MHz
-
50
s
30 - 40 MHz
-
90
s
25 - 30 MHz
-
120
s
Output Jitter (cycle-to-cycle) for any DLL Clock Output(1)
TOJITCC
± 60
ps
Phase Offset between CLKIN and CLKO(2)
TPHIO
± 100
ps
Phase Offset between Clock Outputs on the DLL(3)
TPHOO
± 140
ps
Maximum Phase Difference between CLKIN and
CLKO(4)
TPHIOM
± 160
ps
Maximum Phase Difference between Clock Outputs on
the DLL(5)
TPHOOM
± 200
ps
Notes:
1.
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock, excluding input clock jitter.
2.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
3.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
4.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
5.
Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
6.
All specifications correspond to Commercial Operating Temperatures (0°C to +85°C).
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV200-6FG256C | 功能描述:IC FPGA 2.5V C-TEMP 256-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV200-6FG256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV200-6FG456C | 功能描述:IC FPGA 2.5V C-TEMP 456-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCV200-6FG456I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
| XCV200-6PQ240C | 功能描述:IC FPGA 2.5V C-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
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