- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4196 > XCV1600E-8FG900C (Xilinx Inc)IC FPGA 1.8V C-TEMP 900-FBGA PDF資料下載
參數(shù)資料
| 型號： | XCV1600E-8FG900C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 212/233頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 900-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 7776 |
| 邏輯元件/單元數(shù)： | 34992 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 700 |
| 門數(shù)： | 2188742 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 900-BBGA |
| 供應商設備封裝： | 900-FBGA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁當前第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁
Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
2
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
The output buffer and all of the IOB control signals have
independent polarity controls.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to VCCO with
the exception of LVCMOS18, LVCMOS25, GTL, GTL+,
LVDS, and LVPECL.
Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-imped-
ance state. The pull-down resistors and the weak-keeper
circuits are inactive, but I/Os can optionally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.
All Virtex-E IOBs support IEEE 1149.1-compatible Bound-
ary Scan testing.
Input Path
The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can be used in close prox-
imity to each other. See I/O Banking.
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 – 100 k
Ω.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate VREF voltage must be
provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Table 1: Supported I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Board
Termination
Voltage (VTT)
LVTTL
3.3
N/A
LVCMOS2
2.5
N/A
LVCMOS18
1.8
N/A
SSTL3 I & II
3.3
N/A
1.50
SSTL2 I & II
2.5
N/A
1.25
GTL
N/A
0.80
1.20
GTL+
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
CTT
3.3
N/A
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
N/A
PCI66_3
3.3
N/A
BLVDS & LVDS
2.5
N/A
LVPECL
3.3
N/A
相關PDF資料 |
PDF描述 |
|---|---|
| IDT71016NS15PHG | IC SRAM 1MBIT 15NS 44TSOP |
| XCV1600E-7FG900I | IC FPGA 1.8V I-TEMP 900-FBGA |
| IDT71016NS12PHG | IC SRAM 1MBIT 12NS 44TSOP |
| XC4VLX160-10FF1513I | IC FPGA VIRTEX-4LX 1513FFBGA |
| XC4VLX160-11FFG1513C | IC FPGA VIRTEX-4LX 160K 1513FBGA |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV1600E-8FG900I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV1600E-8HQ240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV1600E-8HQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV200 | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex? 2.5 V Field Programmable Gate Arrays |
| XCV2000E | 制造商:XILINX 制造商全稱:XILINX 功能描述:Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復。