- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4195 > XCV1600E-8FG1156C (Xilinx Inc)IC FPGA 1.8V C-TEMP 1156-FBGA PDF資料下載
參數(shù)資料
| 型號： | XCV1600E-8FG1156C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 152/233頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 1.8V C-TEMP 1156-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標準包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 7776 |
| 邏輯元件/單元數(shù)： | 34992 |
| RAM 位總計： | 589824 |
| 輸入/輸出數(shù)： | 724 |
| 門數(shù)： | 2188742 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 1156-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1156-FBGA（35x35） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁當前第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁第187頁第188頁第189頁第190頁第191頁第192頁第193頁第194頁第195頁第196頁第197頁第198頁第199頁第200頁第201頁第202頁第203頁第204頁第205頁第206頁第207頁第208頁第209頁第210頁第211頁第212頁第213頁第214頁第215頁第216頁第217頁第218頁第219頁第220頁第221頁第222頁第223頁第224頁第225頁第226頁第227頁第228頁第229頁第230頁第231頁第232頁第233頁
Virtex-E 1.8 V Field Programmable Gate Arrays
R
DS022-2 (v3.0) March 21, 2014
Module 2 of 4
Production Product Specification
19
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
mits the internal storage elements to begin changing state
in response to the logic and the user clock.
The relative timing of these events can be changed. In addi-
tion, the GTS, GSR, and GWE events can be made depen-
dent on the DONE pins of multiple devices all going High,
forcing the devices to start synchronously. The sequence
can also be paused at any stage until lock has been
achieved on any or all DLLs.
Readback
The configuration data stored in the Virtex-E configuration
memory can be readback for verification. Along with the
configuration data it is possible to readback the contents all
flip-flops/latches, LUT RAMs, and block RAMs. This capa-
bility is used for real-time debugging. For more detailed
information, see application note XAPP138 “Virtex FPGA
Series Configuration and Readback”.
Design Considerations
This section contains more detailed design information on
the following features.
Delay-Locked Loop . . . see page 19
BlockRAM . . . see page 24
SelectI/O . . . see page 31
Using DLLs
The Virtex-E FPGA series provides up to eight fully digital
dedicated on-chip Delay-Locked Loop (DLL) circuits which
provide zero propagation delay, low clock skew between
output clock signals distributed throughout the device, and
advanced clock domain control. These dedicated DLLs can
be used to implement several circuits which improve and
simplify system level design.
Introduction
As FPGAs grow in size, quality on-chip clock distribution
becomes increasingly important. Clock skew and clock
delay impact device performance and the task of managing
clock skew and clock delay with conventional clock trees
becomes more difficult in large devices. The Virtex-E series
of devices resolve this potential problem by providing up to
eight fully digital dedicated on-chip DLL circuits, which pro-
vide zero propagation delay and low clock skew between
output clock signals distributed throughout the device.
Each DLL can drive up to two global clock routing networks
within the device. The global clock distribution network min-
imizes clock skews due to loading differences. By monitor-
ing a sample of the DLL output clock, the DLL can
compensate for the delay on the routing network, effectively
eliminating the delay from the external input port to the indi-
vidual clock loads within the device.
In addition to providing zero delay with respect to a user
source clock, the DLL can provide multiple phases of the
source clock. The DLL can also act as a clock doubler or it
can divide the user source clock by up to 16.
Clock multiplication gives the designer a number of design
alternatives. For instance, a 50 MHz source clock doubled
by the DLL can drive an FPGA design operating at 100
MHz. This technique can simplify board design because the
clock path on the board no longer distributes such a
high-speed signal. A multiplied clock also provides design-
ers the option of time-domain-multiplexing, using one circuit
twice per clock cycle, consuming less area than two copies
of the same circuit. Two DLLs in can be connected in series
to increase the effective clock multiplication factor to four.
The DLL can also act as a clock mirror. By driving the DLL
output off-chip and then back in again, the DLL can be used
to deskew a board level clock between multiple devices.
In order to guarantee the system clock establishes prior to
the device “waking up,” the DLL can delay the completion of
the device configuration process until after the DLL
achieves lock.
By taking advantage of the DLL to remove on-chip clock
delay, the designer can greatly simplify and improve system
level design involving high-fanout, high-performance clocks.
Library DLL Symbols
Figure 21 shows the simplified Xilinx library DLL macro
symbol, BUFGDLL. This macro delivers a quick and effi-
cient way to provide a system clock with zero propagation
the two library DLL primitives. These symbols provide
access to the complete set of DLL features when imple-
menting more complex applications.
Figure 21: Simplified DLL Macro Symbol BUFGDLL
0ns
ds022_25_121099
O
I
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCV1600E-7FG1156I | IC FPGA 1.8V I-TEMP 1156-FBGA |
| IDT6116SA25SOG | IC SRAM 16KBIT 25NS 24SOIC |
| ABC60DRYN-S93 | CONN EDGECARD 120PS DIP .100 SLD |
| IDT6116SA20SOG | IC SRAM 16KBIT 20NS 24SOIC |
| ABC60DRYH-S93 | CONN EDGECARD 120PS DIP .100 SLD |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCV1600E-8FG1156I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV1600E-8FG240C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
| XCV1600E-8FG240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
| XCV1600E-8FG680C | 功能描述:IC FPGA 1.8V C-TEMP 680-FBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-E 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
| XCV1600E-8FG680I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Virtex-E 1.8 V Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。