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| 型號(hào)： | XCV1000E-6FG1156I |
| 廠(chǎng)商： | Xilinx Inc |
| 文件頁(yè)數(shù)： | 212/233頁(yè) |
| 文件大小： | 0K |
| 描述： | IC FPGA 1.8V I-TEMP 1156-FBGA |
| 產(chǎn)品變化通告： | FPGA Family Discontinuation 18/Apr/2011 |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | Virtex®-E |
| LAB/CLB數(shù)： | 6144 |
| 邏輯元件/單元數(shù)： | 27648 |
| RAM 位總計(jì)： | 393216 |
| 輸入/輸出數(shù)： | 660 |
| 門(mén)數(shù)： | 1569178 |
| 電源電壓： | 1.71 V ~ 1.89 V |
| 安裝類(lèi)型： | 表面貼裝 |
| 工作溫度： | -40°C ~ 100°C |
| 封裝/外殼： | 1156-BBGA |
| 供應(yīng)商設(shè)備封裝： | 1156-FBGA（35x35） |
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Virtex-E 1.8 V Field Programmable Gate Arrays
R
Module 2 of 4
DS022-2 (v3.0) March 21, 2014
2
Production Product Specification
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
In addition to the CLK and CE control signals, the three
flip-flops share a Set/Reset (SR). For each flip-flop, this sig-
nal can be independently configured as a synchronous Set,
a synchronous Reset, an asynchronous Preset, or an asyn-
chronous Clear.
The output buffer and all of the IOB control signals have
independent polarity controls.
All pads are protected against damage from electrostatic
discharge (ESD) and from over-voltage transients. After
configuration, clamping diodes are connected to VCCO with
the exception of LVCMOS18, LVCMOS25, GTL, GTL+,
LVDS, and LVPECL.
Optional pull-up, pull-down and weak-keeper circuits are
attached to each pad. Prior to configuration all outputs not
involved in configuration are forced into their high-imped-
ance state. The pull-down resistors and the weak-keeper
circuits are inactive, but I/Os can optionally be pulled up.
The activation of pull-up resistors prior to configuration is
controlled on a global basis by the configuration mode pins.
If the pull-up resistors are not activated, all the pins are in a
high-impedance state. Consequently, external pull-up or
pull-down resistors must be provided on pins required to be
at a well-defined logic level prior to configuration.
All Virtex-E IOBs support IEEE 1149.1-compatible Bound-
ary Scan testing.
Input Path
The Virtex-E IOB input path routes the input signal directly
to internal logic and/ or through an optional input flip-flop.
An optional delay element at the D-input of this flip-flop elim-
inates pad-to-pad hold time. The delay is matched to the
internal clock-distribution delay of the FPGA, and when
used, assures that the pad-to-pad hold time is zero.
Each input buffer can be configured to conform to any of the
low-voltage signalling standards supported. In some of
these standards the input buffer utilizes a user-supplied
threshold voltage, VREF. The need to supply VREF imposes
constraints on which standards can be used in close prox-
imity to each other. See I/O Banking.
There are optional pull-up and pull-down resistors at each
user I/O input for use after configuration. Their value is in
the range 50 – 100 k
Ω.
Output Path
The output path includes a 3-state output buffer that drives
the output signal onto the pad. The output signal can be
routed to the buffer directly from the internal logic or through
an optional IOB output flip-flop.
The 3-state control of the output can also be routed directly
from the internal logic or through a flip-flip that provides syn-
chronous enable and disable.
Each output driver can be individually programmed for a
wide range of low-voltage signalling standards. Each output
buffer can source up to 24 mA and sink up to 48 mA. Drive
strength and slew rate controls minimize bus transients.
In most signalling standards, the output High voltage
depends on an externally supplied VCCO voltage. The need
to supply VCCO imposes constraints on which standards
can be used in close proximity to each other. See I/O Bank-
An optional weak-keeper circuit is connected to each out-
put. When selected, the circuit monitors the voltage on the
pad and weakly drives the pin High or Low to match the
input signal. If the pin is connected to a multiple-source sig-
nal, the weak keeper holds the signal in its last state if all
drivers are disabled. Maintaining a valid logic level in this
way eliminates bus chatter.
Since the weak-keeper circuit uses the IOB input buffer to
monitor the input level, an appropriate VREF voltage must be
provided if the signalling standard requires one. The provi-
sion of this voltage must comply with the I/O banking rules.
I/O Banking
Some of the I/O standards described above require VCCO
and/or VREF voltages. These voltages are externally sup-
plied and connected to device pins that serve groups of
IOBs, called banks. Consequently, restrictions exist about
which I/O standards can be combined within a given bank.
Table 1: Supported I/O Standards
I/O
Standard
Output
VCCO
Input
VCCO
Input
VREF
Board
Termination
Voltage (VTT)
LVTTL
3.3
N/A
LVCMOS2
2.5
N/A
LVCMOS18
1.8
N/A
SSTL3 I & II
3.3
N/A
1.50
SSTL2 I & II
2.5
N/A
1.25
GTL
N/A
0.80
1.20
GTL+
N/A
1.0
1.50
HSTL I
1.5
N/A
0.75
HSTL III & IV
1.5
N/A
0.90
1.50
CTT
3.3
N/A
1.50
AGP-2X
3.3
N/A
1.32
N/A
PCI33_3
3.3
N/A
PCI66_3
3.3
N/A
BLVDS & LVDS
2.5
N/A
LVPECL
3.3
N/A
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| XCV1000E-6FG240C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Virtex⑩-E 1.8 V Field Programmable Gate Arrays |
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| XCV1000E6FG680C | 制造商:XILINX 功能描述:New |
| XCV1000E-6FG680C | 功能描述:IC FPGA 1.8V C-TEMP 680-FGBA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5 |
| XCV1000E-6FG680I | 功能描述:IC FPGA 1.8V I-TEMP 680-FGBA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:Virtex®-E 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標(biāo)準(zhǔn)包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計(jì):3200 輸入/輸出數(shù):80 門(mén)數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55） |
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