參數(shù)資料
型號： XCS30XL-4VQ100I
廠商： Xilinx Inc
文件頁數(shù)： 38/83頁
文件大小： 0K
描述： IC FPGA 3.3V I-TEMP HP 100VQFP
產(chǎn)品變化通告： Product Discontinuation 26/Oct/2011
標準包裝： 90
系列： Spartan®-XL
LAB/CLB數(shù)： 576
邏輯元件/單元數(shù)： 1368
RAM 位總計： 18432
輸入/輸出數(shù)： 77
門數(shù)： 30000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 100-TQFP
供應商設(shè)備封裝： 100-VQFP（14x14）
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
43
Product Specification
R
Product Obsolete/Under Obsolescence
Spartan Family DC Characteristics Over Operating Conditions
Spartan Family Global Buffer Switching Characteristic Guidelines
All devices are 100% functionally tested. Internal timing
parameters are derived from measuring internal test pat-
terns. Listed below are representative values where one
global clock input drives one vertical clock line in each
accessible column, and where all accessible IOB and CLB
flip-flops are clocked by the global clock net.
When fewer vertical clock lines are connected, the clock dis-
tribution is faster; when multiple clock lines per column are
driven from the same global clock, the delay is longer. For
more specific, more precise, and worst-case guaranteed
data, reflecting the actual routing structure, use the values
provided by the static timing analyzer (TRCE in the Xilinx
Development System) and back-annotated to the simulation
netlist. These path delays, provided as a guideline, have
been extracted from the static timing analyzer report. All
timing parameters assume worst-case operating conditions
(supply voltage and junction temperature).
Symbol
Description
Min
Max
Units
VOH
High-level output voltage @ IOH = –4.0 mA, VCC min
TTL outputs
2.4
-
V
High-level output voltage @ IOH = –1.0 mA, VCC min
CMOS outputs
VCC – 0.5
-
V
VOL
Low-level output voltage @ IOL = 12.0 mA, VCC min(1)
TTL outputs
-
0.4
V
CMOS outputs
-
0.4
V
VDR
Data retention supply voltage (below which configuration data may be lost)
3.0
-
V
ICCO
Quiescent FPGA supply current(2)
Commercial
-
3.0
mA
Industrial
-
6.0
mA
IL
Input or output leakage current
–10
+10
μA
CIN
Input capacitance (sample tested)
-
10
pF
IRPU
Pad pull-up (when selected) @ VIN = 0V (sample tested)
0.02
0.25
mA
IRPD
Pad pull-down (when selected) @ VIN = 5V (sample tested)
0.02
-
mA
Notes:
1.
With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2.
With no output current loads, no active input pull-up resistors, all package pins at VCC or GND, and the FPGA configured with a Tie
option.
Symbol
Description
Device
Speed Grade
Units
-4
-3
Max
TPG
From pad through Primary buffer, to any clock K
XCS05
2.0
4.0
ns
XCS10
2.4
4.3
ns
XCS20
2.8
5.4
ns
XCS30
3.2
5.8
ns
XCS40
3.5
6.4
ns
TSG
From pad through Secondary buffer, to any clock K
XCS05
2.5
4.4
ns
XCS10
2.9
4.7
ns
XCS20
3.3
5.8
ns
XCS30
3.6
6.2
ns
XCS40
3.9
6.7
ns
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