- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4058 > XCS30-3PQ208C (Xilinx Inc)IC FPGA 5V C-TEMP 208-PQFP PDF資料下載
參數(shù)資料
| 型號： | XCS30-3PQ208C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 18/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 5V C-TEMP 208-PQFP |
| 產(chǎn)品變化通告： | Spartan,Virtex FPGA/SCD Discontinuation 18/Oct/2010 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | Spartan® |
| LAB/CLB數(shù)： | 576 |
| 邏輯元件/單元數(shù)： | 1368 |
| RAM 位總計(jì)： | 18432 |
| 輸入/輸出數(shù)： | 169 |
| 門數(shù)： | 30000 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 208-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 208-PQFP（28x28） |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當(dāng)前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v2.0) March 1, 2013
25
Product Specification
R
Product Obsolete/Under Obsolescence
Power-down retains the configuration, but loses all data
stored in the device flip-flops. All inputs are interpreted as
Low, but the internal combinatorial logic is fully functional.
Make sure that the combination of all inputs Low and all
flip-flops set or reset in your design will not generate internal
oscillations, or create permanent bus contention by activat-
ing internal bus drivers with conflicting data onto the same
long line.
During configuration, the PWRDWN pin must be High. If the
Power Down state is entered before or during configuration,
the device will restart configuration once the PWRDWN sig-
nal is removed. Note that the configuration pins are affected
by Power Down and may not reflect their normal function. If
there is an external pull-up resistor on the DONE pin, it will
be High during Power Down even if the device is not yet
configured. Similarly, if PWRDWN is asserted before config-
uration is completed, the INIT pin will not indicate status
information.
Note that the PWRDWN pin is not part of the Boundary
Scan chain. Therefore, the Spartan-XL family has a sepa-
rate set of BSDL files than the 5V Spartan family. Boundary
scan logic is not usable during Power Down.
Configuration and Test
Configuration is the process of loading design-specific pro-
gramming data into one or more FPGAs to define the func-
tional
operation
of
the
internal
blocks
and
their
interconnections. This is somewhat like loading the com-
mand registers of a programmable peripheral chip.
Spartan/XL devices use several hundred bits of configura-
tion data per CLB and its associated interconnects. Each
configuration bit defines the state of a static memory cell
that controls either a function look-up table bit, a multiplexer
input, or an interconnect pass transistor. The Xilinx develop-
ment system translates the design into a netlist file. It auto-
matically partitions, places and routes the logic and
generates the configuration data in PROM format.
Configuration Mode Control
5V Spartan devices have two configuration modes.
MODE = 1 sets Slave Serial mode
MODE = 0 sets Master Serial mode
3V Spartan-XL devices have three configuration modes.
M1/M0 = 11 sets Slave Serial mode
M1/M0 = 10 sets Master Serial mode
M1/M0 = 0X sets Express mode
In addition to these modes, the device can be configured
through the Boundary Scan logic (See "Configuration
The Mode pins are sampled prior to starting configuration to
determine the configuration mode. After configuration,
these pin are unused. The Mode pins have a weak pull-up
resistor turned on during configuration. With the Mode pins
High, Slave Serial mode is selected, which is the most pop-
ular configuration mode. Therefore, for the most common
configuration mode, the Mode pins can be left unconnected.
If the Master Serial mode is desired, the MODE/M0 pin
should be connected directly to GND, or through a
pull-down resistor of 1 K
Ω or less.
During configuration, some of the I/O pins are used tempo-
rarily for the configuration process. All pins used during con-
Figure 23: PWRDWN Pulse Timing
Power Down Mode
50 ns
TPWDW
TPWD
TPWDW
Outputs
PWRDWN
Description
Power Down Time
Power Down Pulse Width
Symbol
Min
50 ns
DS060_23_041901
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 65801-166LF | CLINCHER RECEPTACLE ASSY GOLD |
| XCS30-3BG256C | IC FPGA 5V C-TEMP 256-PBGA |
| MPC860PVR80D4R2 | IC MPU POWERQUICC 80MHZ 357PBGA |
| IDT71T75602S133BG8 | IC SRAM 18MBIT 133MHZ 119BGA |
| IDT71T75602S100BGG8 | IC SRAM 18MBIT 100MHZ 119BGA |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS30-3PQ208I | 功能描述:IC FPGA 5V I-TEMP 208-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30-3PQ208I0167 | 制造商:Xilinx 功能描述: |
| XCS30-3PQ240C | 功能描述:IC FPGA 5V C-TEMP 240-PQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Spartan® 標(biāo)準(zhǔn)包裝:1 系列:Kintex-7 LAB/CLB數(shù):25475 邏輯元件/單元數(shù):326080 RAM 位總計(jì):16404480 輸入/輸出數(shù):350 門數(shù):- 電源電壓:0.97 V ~ 1.03 V 安裝類型:表面貼裝 工作溫度:0°C ~ 85°C 封裝/外殼:900-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:900-FCBGA（31x31） 其它名稱:122-1789 |
| XCS30-3PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS30-3PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。