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    參數(shù)資料
    型號(hào): XCS20XL-3BG256C
    廠商: Xilinx, Inc.
    英文描述: Spartan and Spartan-XL Families Field Programmable Gate Arrays
    中文描述: 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
    文件頁(yè)數(shù): 61/82頁(yè)
    文件大?。?/td> 863K
    代理商: XCS20XL-3BG256C
    Spartan and Spartan-XL Families Field Programmable Gate Arrays
    64
    DS060 (v1.6) September 19, 2001
    1-800-255-7778
    Product Specification
    R
    SGCK1 -
    SGCK4
    (Spartan)
    Weak
    Pull-up
    (except
    SGCK4
    is DOUT)
    I or I/O
    Four Secondary Global inputs each drive a dedicated internal global net with short
    delay and minimal skew. These internal global nets can also be driven from
    internal logic. If not used to drive a global net, any of these pins is a
    user-programmable I/O pin.
    The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global
    Buffers. Any input pad symbol connected directly to the input of a BUFGS symbol
    is automatically placed on one of these pins.
    GCK1 -
    GCK8
    (Spartan-XL)
    Weak
    Pull-up
    (except
    GCK6 is
    DOUT)
    I or I/O
    Eight Global inputs each drive a dedicated internal global net with short delay and
    minimal skew. These internal global nets can also be driven from internal logic. If
    not used to drive a global net, any of these pins is a user-programmable I/O pin.
    The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew
    Buffers. Any input pad symbol connected directly to the input of a BUFGLS symbol
    is automatically placed on one of these pins.
    CS1
    (Spartan-XL)
    I
    I/O
    During Express configuration, CS1 is used as a serial-enable signal for
    daisy-chaining.
    D0-D7
    (Spartan-XL)
    I
    I/O
    During Express configuration, these eight input pins receive configuration data.
    After configuration, they are user-programmable I/O pins.
    DIN
    I
    I/O
    During Slave Serial or Master Serial configuration, DIN is the serial configuration
    data input receiving data on the rising edge of CCLK. After configuration, DIN is a
    user-programmable I/O pin.
    DOUT
    O
    I/O
    During Slave Serial or Master Serial configuration, DOUT is the serial
    configuration data output that can drive the DIN of daisy-chained slave FPGAs.
    DOUT data changes on the falling edge of CCLK, one-and-a-half CCLK periods
    after it was received at the DIN input.
    In Spartan-XL Express mode, DOUT is the status output that can drive the CS1 of
    daisy-chained FPGAs, to enable and disable downstream devices.
    After configuration, DOUT is a user-programmable I/O pin.
    Unrestricted User-Programmable I/O Pins
    I/O
    Weak
    Pull-up
    I/O
    These pins can be configured to be input and/or output after configuration is
    completed. Before configuration is completed, these pins have an internal
    high-value pull-up resistor network that defines the logic level as High.
    Table 18: Pin Descriptions (Continued)
    Pin Name
    I/O
    During
    Config.
    I/O After
    Config.
    Pin Description
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