參數(shù)資料
型號(hào)： XCS20XL-3BG256C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門(mén)陣列
文件頁(yè)數(shù)： 41/82頁(yè)
文件大?。?/td> 863K
代理商： XCS20XL-3BG256C
Spartan and Spartan-XL Families Field Programmable Gate Arrays
46
DS060 (v1.6) September 19, 2001
1-800-255-7778
Product Specification
R
Spartan CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines (continued)
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan devices and are expressed in nanosec-
onds unless otherwise noted.
Spartan CLB RAM Synchronous (Edge-Triggered) Write Timing
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Dual Port RAM
Size(1)
-4
-3
Units
Min
Max
Min
Max
Write Operation
TWCDS
Address write cycle time (clock K period)
16x1
8.0
-
11.6
-
ns
TWPDS
Clock K pulse width (active edge)
16x1
4.0
-
5.8
-
ns
TASDS
Address setup time before clock K
16x1
1.5
-
2.1
-
ns
TAHDS
Address hold time after clock K
16x1
0
-
0
-
ns
TDSDS
DIN setup time before clock K
16x1
1.5
-
1.6
-
ns
TDHDS
DIN hold time after clock K
16x1
0
-
0
-
ns
TWSDS
WE setup time before clock K
16x1
1.5
-
1.6
-
ns
TWHDS
WE hold time after clock K
16x1
0
-
0
-
ns
TWODS
Data valid after clock K
16x1
-
6.5
-
7.0
ns
Notes:
1.
Read Operation timing for 16 x 1 dual-port RAM option is identical to 16 x 2 single-port RAM timing
Single Port
Dual Port
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSS
TDHS
TASS
TAHS
TWSS
TWPS
TWHS
TWSDS
TWHDS
TWOS
TILO
DS060_34_011300
WCLK (K)
WE
ADDRESS
DATA IN
DATA OUT
OLD
NEW
TDSDS
TDHDS
TASDS
TAHDS
TWPDS
TWODS
TILO
相關(guān)PDF資料
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XCS20XL-3BG256I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL FPGA
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XCS20XL-3BG84C 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
XCS20XL-3BG84I 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays
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