- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375017 > XCS10XL (Xilinx, Inc.) Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) PDF資料下載
參數(shù)資料
| 型號： | XCS10XL |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| 中文描述： | 現(xiàn)場可編程門陣列（現(xiàn)場可編程門陣列） |
| 文件頁數(shù)： | 50/66頁 |
| 文件大?。?/td> | 716K |
| 代理商： | XCS10XL |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁當(dāng)前第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-50
DS060 (v1.5) March 2, 2000
Spartan-XL Pin-to-Pin Output Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading.
Spartan-XL Output Flip-Flop, Clock-to-Out
Note 1: Output delays are representative values where one global clock input drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are clocked by the global clock net.
Note 2: Output timing is measured at ~50% V
CC
threshold with 50 pF external capacitive load.
Spartan-XL Pin-to-Pin Input Parameter Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Pin-to-pin timing parameters are derived from measuring external and internal test patterns and are
guaranteed over worst-case operating conditions (supply voltage and junction temperature). Listed below are representative
values for typical pin locations and normal clock loading.
Spartan-XL Setup and Hold
Note 3: Setup time is measured with the fastest route and the lightest load. Hold time is measured using the furthest distance and a
reference load of one clock pin per IOB/CLB.
Speed Grade
Description
Global Clock to Output using OFF
Fast
-5
-4
Units
Symbol
Device
Max
Max
T
ICKOF
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.6
4.9
5.2
5.5
5.8
5.2
5.5
5.8
6.2
6.5
ns
ns
ns
ns
ns
Slew Rate Adjustment
For Output SLOW option add
OFF = Output Flip Flop
T
SLOW
All Devices
1.5
1.7
ns
Speed Grade
Description
Input Setup/Hold Times Using Global Clock and IFF
No Delay
-5
Min
-4
Min
Units
Symbol
Device
T
SUF
/T
HF
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
1.1/2.0
1.0/2.2
0.9/2.4
0.8/2.6
0.7/2.8
3.9/0.0
4.1/0.0
4.3/0.0
4.5/0.0
4.7/0.0
1.6/2.6
1.5/2.8
1.4/3.0
1.3/3.2
1.2/3.4
5.1/0.0
5.3/0.0
5.5/0.0
5.7/0.0
5.9/0.0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Full Delay
T
SU
/T
H
IFF = Input Flip-Flop or Latch
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS20XL | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| XCS30XL | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| XCS10 | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| XCS20 | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
| XCS40 | Field Programmable Gate Arrays(現(xiàn)場可編程門陣列) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS10XL-3BG100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG144C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG144I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS10XL-3BG208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。