參數(shù)資料
型號(hào)： XCS10XL
廠商： Xilinx, Inc.
英文描述： Field Programmable Gate Arrays(現(xiàn)場(chǎng)可編程門(mén)陣列)
中文描述： 現(xiàn)場(chǎng)可編程門(mén)陣列（現(xiàn)場(chǎng)可編程門(mén)陣列）
文件頁(yè)數(shù)： 5/66頁(yè)
文件大?。?/td> 716K
代理商： XCS10XL
R
DS060 (v1.5) March 2, 2000
4-5
Spartan and Spartan-XL Families Field Programmable Gate Arrays
CLB Signal Flow Control
In addition to the H-LUT input control multiplexers (shown
in box "A" of
Figure 2 on page 3
) there are signal flow con-
trol multiplexers (shown in box "B" of
Figure 2
) which select
the signals which drive the flip-flop inputs and the combina-
torial CLB outputs (X and Y).
Each flip-flop input is driven from a 4:1 multiplexer which
selects among the three LUT outputs and DIN as the data
source.
Each combinatorial output is driven from a 2:1 multiplexer
which selects between two of the LUT outputs. The X out-
put can be driven from the F-LUT or H-LUT, the Y output
from G-LUT or H-LUT.
Control Signals
There are four signal control multiplexers on the input of the
CLB. These multiplexers allow the internal CLB control sig-
nals (H1, DIN, SR, and EC in
Figure 2
and
Figure 4
) to be
driven from any of the four general control inputs (C1 - C4
in
Figure 4
) into the CLB. Any of these inputs can drive any
of the four internal control signals.
The four internal control signals are:
EC - Enable Clock
SR - Asynchronous Set/Reset or H function generator
Input 0
DIN - Direct In or H function generator Input 2
H1 - H function generator Input 1.
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 5 on
page 6
shows a simplified functional block diagram of the
Spartan/XL IOB.
IOB Input Signal Path
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in
Figure 5
) or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in
Table 3
,
and a simplified block diagram of the register can be seen
in
Figure 6
.
Figure 4: CLB Control Signal Interface
C1
C2
C3
C4
DIN
H1
SR
EC
Multiplexer Controlled
by Configuration Program
Rev 1.1
Table 3: Input Register Functionality
Mode
CK
X
EC
X
D
X
Q
SR
Power-Up or
GSR
Flip-Flop
__/
0
1
0
X
1*
X
1*
1*
0
D
X
X
D
X
D
Q
Q
D
Q
Latch
Both
Legend:
X
__/
SR
0*
1*
Don
’
t care
Rising edge (clock not inverted)
Set or Reset value. Reset is default.
Input is Low or unconnected (default value)
Input is High or unconnected (default value)
D
Q
SD
RD
GSR
D
EC
CK
Q
Multiplexer Controlled
by Configuration Program
Rev 1.1
Vcc
Figure 6: IOB Flip-Flop/Latch Functional Block
Diagram
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