參數(shù)資料
型號(hào): XCS10XL-4PC84C
廠商: XILINX INC
元件分類: FPGA
英文描述: Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述: FPGA, 196 CLBS, 3000 GATES, 217 MHz, PQCC84
封裝: PLASTIC, LCC-84
文件頁數(shù): 31/83頁
文件大?。?/td> 770K
代理商: XCS10XL-4PC84C
Spartan and Spartan-XL FPGA Families Data Sheet
DS060 (v1.8) June 26, 2008
37
Product Specification
R
Configuration Through the Boundary Scan
Pins
Spartan/XL devices can be configured through the bound-
ary scan pins. The basic procedure is as follows:
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input.
Wait for INIT to go High.
Sequence the boundary scan Test Access Port to the
SHIFT-DR state.
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note, "Boundary Scan in FPGA Devices." This application
note applies to Spartan and Spartan-XL devices.
Figure 31: Start-up Timing
UCLK_SYNC
UCLK_NOSYNC
CCLK_SYNC
CCLK_NOSYNC
CCLK
GSR Active
UCLK Period
DONE IN
Di
Di+1
Di+2
Di
Di+1
Di+2
U2
U3
U4
U2
U3
U4
U2
U3
U4
C1
Synchronization
Uncertainty
Di
Di+1
Di
Di+1
DONE
I/O
GSR Active
DONE
I/O
GSR Active
DONE
C1
C2
C1
U2
C3
C4
C2
C3
C4
C2
C3
C4
I/O
GSR Active
DONE
I/O
F = Finished, no more
configuration clocks needed
Daisy-chain lead device
must have latest F
Heavy lines describe
default timing
CCLK Period
Length Count Match
F
DS060_39_082801
C1, C2 or C3
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