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參數(shù)資料
| 型號： | XCS05XL-4PC84C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/83頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA 3.3V C-TEMP 84-PLCC |
| 標準包裝： | 15 |
| 系列： | Spartan®-XL |
| LAB/CLB數(shù)： | 100 |
| 邏輯元件/單元數(shù)： | 238 |
| RAM 位總計： | 3200 |
| 輸入/輸出數(shù)： | 61 |
| 門數(shù)： | 5000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC |
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Spartan and Spartan-XL FPGA Families Data Sheet
12
DS060 (v2.0) March 1, 2013
Product Specification
R
Product Obsolete/Under Obsolescence
Double-Length Lines
The double-length lines consist of a grid of metal segments,
each twice as long as the single-length lines: they run past
two CLBs before entering a PSM. Double-length lines are
grouped in pairs with the PSMs staggered, so that each line
goes through a PSM at every other row or column of CLBs
(see Figure 8).
There are four vertical and four horizontal double-length
lines associated with each CLB. These lines provide faster
signal routing over intermediate distances, while retaining
routing flexibility.
Longlines
Longlines form a grid of metal interconnect segments that
run the entire length or width of the array. Longlines are
intended for high fan-out, time-critical signal nets, or nets
that are distributed over long distances.
Each Spartan/XL device longline has a programmable split-
ter switch at its center. This switch can separate the line into
two independent routing channels, each running half the
width or height of the array.
Routing connectivity of the longlines is shown in Figure 8.
The longlines also interface to some 3-state buffers which is
described later in 3-State Long Line Drivers, page 19.
I/O Routing
Spartan/XL devices have additional routing around the IOB
ring. This routing is called a VersaRing. The VersaRing facil-
itates pin-swapping and redesign without affecting board
layout. Included are eight double-length lines, and four long-
lines.
Global Nets and Buffers
The Spartan/XL devices have dedicated global networks.
These networks are designed to distribute clocks and other
high fanout control signals throughout the devices with min-
imal skew.
Four vertical longlines in each CLB column are driven exclu-
sively by special global buffers. These longlines are in addi-
tion to the vertical longlines used for standard interconnect.
In the 5V Spartan devices, the four global lines can be
driven by either of two types of global buffers; Primary
Global buffers (BUFGP) or Secondary Global buffers
(BUFGS). Each of these lines can be accessed by one par-
ticular Primary Global buffer, or by any of the Secondary
Global buffers, as shown in Figure 11. In the 3V
Spartan-XL devices, the four global lines can be driven by
any of the eight Global Low-Skew Buffers (BUFGLS). The
clock pins of every CLB and IOB can also be sourced from
local interconnect.
Figure 10: Programmable Switch Matrix
Six Pass Transistors Per
Switch Matrix Interconnect Point
DS060_10_081100
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