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參數(shù)資料
| 型號： | XCS05XL-3PC84I |
| 廠商： | XILINX INC |
| 元件分類： | FPGA |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | FPGA, 100 CLBS, 2000 GATES, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 32/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05XL-3PC84I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-32
DS060 (v1.5) March 2, 2000
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Readback of Spartan-XL Express mode bitstreams results
in data that does not resemble the original bitstream,
because the bitstream format differs from other modes.
Spartan/XL Readback does not use any dedicated pins, but
uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, instantiate the
READBACK library symbol and attach the appropriate pad
symbols, as shown in
Figure 31
.
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
Readback Options
Readback options are: Readback Capture, Readback
Abort, and Clock Select. They are set with the bitstream
generation software.
Readback Capture
When the Readback Capture option is selected, the \ data
stream includes sampled values of CLB and IOB signals.
The rising edge of RDBK.TRIG latches the inverted values
of the four CLB outputs, the IOB output flip-flops and the
input signals I1 and I2. Note that while the bits describing
configuration (interconnect, function generators, and RAM
content) are
not
inverted, the CLB and IOB output signals
are
inverted. RDBK.TRIG is located in the lower-left corner
of the device.
When the Readback Capture option is not selected, the val-
ues of the capture bits reflect the configuration data origi-
nally written to those memory locations. If the RAM
capability of the CLBs is used, RAM data are available in
Readback, since they directly overwrite the F and G func-
tion-table configuration of the CLB.
Readback Abort
When the Readback Abort option is selected, a
High-to-Low transition on RDBK.TRIG terminates the
Readback operation and prepares the logic to accept
another trigger.
After an aborted Readback, additional clocks (up to one
Readback clock per configuration frame) may be required
to re-initialize the control logic. The status of Readback is
indicated by the output control net RDBK.RIP. RDBK.RIP is
High whenever a readback is in progress.
Clock Select
CCLK is the default clock. However, the user can insert
another clock on RDBK.CLK. Readback control and data
are clocked on rising edges of RDBK.CLK. If Readback
must be inhibited for security reasons, the Readback con-
trol nets are simply not connected. RDBK.CLK is located in
the lower right chip corner.
Violating the Maximum High and Low Time
Specification for the Readback Clock
The Readback clock has a maximum High and Low time
specification. In some cases, this specification cannot be
met. For example, if a processor is controlling Readback,
an interrupt may force it to stop in the middle of a readback.
This necessitates stopping the clock, and thus violating the
specification.
The specification is mandatory only on clocking data at the
end of a frame prior to the next start bit. The transfer mech-
anism will load the data to a shift register during the last six
clock cycles of the frame, prior to the start bit of the follow-
ing frame. This loading process is dynamic, and is the
source of the maximum High and Low time requirements.
Figure 31: Readback Schematic Example
READBACK
DATA
RIP
TRIG
CLK
READ_DATA
OBUF
READ_TRIGGER
IBUF
s1786_01
IF UNCONNECTED,
DEFAULT IS CCLK
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