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參數資料
| 型號： | XCS05XL-3PC240I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現場可編程門陣列 |
| 文件頁數： | 51/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05XL-3PC240I |
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R
DS060 (v1.5) March 2, 2000
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4-51
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Capacitive Load Factor
Figure 33
shows the relationship between I/O output delay
and load capacitance. It allows a user to adjust the speci-
fied output delay if the load capacitance is different than
50 pF. For example, if the actual load capacitance is
120 pF, add 2.5 ns to the specified delay. If the load capac-
itance is 20 pF, subtract 0.8 ns from the specified output
delay.
Figure 33
is usable over the specified operating con-
ditions of voltage and temperature and is independent of
the output slew rate control.
Spartan-XL IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Internal timing parameters are derived from measuring internal test patterns. Listed below are
representative values. For more specific, more precise, and worst-case guaranteed data, use the values reported by the
static timing analyzer (TRCE in the Xilinx Development System) and back-annotated to the simulation netlist. These path
delays, provided as a guideline, have been extracted from the static timing analyzer report. All timing parameters assume
worst-case operating conditions (supply voltage and junction temperature).
Note 1: Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the
clock input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Note 2: Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
X8257
-2
0
20
40
Capacitance (pF)
60
80
D
100 120 140
-1
0
1
2
3
Figure 33: Delay Factor at Various Capacitive Loads
Speed Grade
Description
-5
-4
Units
Symbol
Device
Min
Max
Min
Max
Setup Times
Clock Enable (EC) to Clock (IK)
Pad to Clock (IK), no delay
Pad to Fast Capture Latch Enable (OK), no delay
Hold Times
All Hold Times
Propagation Delays
Pad to I1, I2
Pad to I1, I2 via transparent input latch, no delay
Clock (IK) to I1, I2 (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
Delay Adder for Input with Full Delay Option
T
PICKD
= T
PICK
+ T
Delay
T
PDLI
= T
PLI
+ T
Delay
T
ECIK
T
PICK
T
POCK
All devices
All devices
All devices
0.0
1.0
0.7
0.0
1.2
0.8
ns
ns
ns
All devices
0.0
0.0
ns
T
PID
T
PLI
T
IKRI
T
IKLI
All devices
All devices
All devices
All devices
0.9
2.1
1.0
1.1
1.1
2.5
1.1
1.2
ns
ns
ns
ns
T
Delay
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
4.0
4.8
5.0
5.5
6.5
4.7
5.6
5.9
6.5
7.6
ns
ns
ns
ns
ns
Global Set/Reset
Minimum GSR pulse width
Delay from GSR input to any Q
T
MRW
T
RRI
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
10.5
11.5
ns
ns
ns
ns
ns
ns
9.0
9.5
10.0
11.0
12.0
10.5
11.0
11.5
12.5
13.5
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相關代理商/技術參數 |
參數描述 |
|---|---|
| XCS05XL-3PC256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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| XCS05XL-3PC280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3PC84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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