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| 型號： | XCS05XL-3CS256I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 23/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05XL-3CS256I |
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R
DS060 (v1.5) March 2, 2000
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4-23
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Master Serial Mode
The Master serial mode uses an internal oscillator to gen-
erate a Configuration Clock (CCLK) for driving potential
slave devices and the Xilinx serial-configuration PROM
(SPROM). The CCLK speed is selectable as either 1 MHz
(default) or 8 MHz. Configuration always starts at the
default slow frequency, then can switch to the higher fre-
quency during the first frame. Frequency tolerance is -50%
to +25%.
In Master Serial mode, the CCLK output of the device
drives a Xilinx SPROM that feeds the FPGA DIN input.
Each rising edge of the CCLK output increments the Serial
PROM internal address counter. The next data bit is put on
the SPROM data output, connected to the FPGA DIN pin.
The FPGA accepts this data on the subsequent rising
CCLK edge.
When used in a daisy-chain configuration the Master Serial
FPGA is placed as the first device in the chain and is
referred to as the lead FPGA. The lead FPGA presents the
preamble data, and all data that overflows the lead device,
on its DOUT pin. There is an internal pipeline delay of 1.5
CCLK periods, which means that DOUT changes on the
falling CCLK edge, and the next FPGA in the daisy chain
accepts data on the subsequent rising CCLK edge. See the
timing diagram in
Figure 24
.
In the bitstream generation software, the user can specify
Fast Configuration Rate, which, starting several bits into the
first frame, increases the CCLK frequency by a factor of
eight. For actual timing values please refer to the specifica-
tion section. Be sure that the serial PROM and slaves are
fast enough to support this data rate. Devices such as
XC3000A and XC3100A do not support the Fast Configura-
tion Rate option.
The SPROM CE input can be driven from either LDC or
DONE. Using LDC avoids potential contention on the DIN
pin, if this pin is configured as user I/O, but LDC is then
restricted to be a permanently High user output after con-
figuration. Using DONE can also avoid contention on DIN,
provided the Early DONE option is invoked.
Figure 25
shows a full master/slave system. The leftmost
device is in Master Serial mode, all other devices in the
chain are in Slave Serial mode.
Serial Data In
CCLK
(Output)
Serial DOUT
(Output)
1
T
DSCK
2
T
CKDS
n
n + 1
n + 2
n
–
3
n
–
2
n
–
1
n
X3223
Notes:
1. At power-up, V
must rise from 2.0V to V
CC
min in less than 25 ms, otherwise delay configuration by pulling PROGRAM
Low until V
is valid.
2. Master Serial mode timing is based on testing in slave mode.
Figure 24: Master Serial Mode Programming Switching Characteristics
Description
Symbol
Min
20
0
Max
Units
ns
ns
CCLK
DIN setup
DIN hold
1
2
T
DSCK
T
CKDS
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| XCS05XL-3CS280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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| XCS05XL-3PC100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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