- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄372886 > XCS05XL-3CS256I (Xilinx, Inc.) Spartan and Spartan-XL Families Field Programmable Gate Arrays PDF資料下載
參數(shù)資料
| 型號(hào)： | XCS05XL-3CS256I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 12/66頁 |
| 文件大小： | 809K |
| 代理商： | XCS05XL-3CS256I |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁當(dāng)前第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-12
DS060 (v1.5) March 2, 2000
The four Primary Global buffers offer the shortest delay and
negligible skew. Four Secondary Global buffers have
slightly longer delay and slightly more skew due to poten-
tially heavier loading, but offer greater flexibility when used
to drive non-clock CLB inputs. The eight Global Low-Skew
buffers in the Spartan-XL devices combine short delay,
negligible skew, and flexibility.
The Primary Global buffers must be driven by the
semi-dedicated pads (PGCK1-4). The Secondary Global
buffers can be sourced by either semi-dedicated pads
(SGCK1-4) or internal nets. Each corner of the device has
one Primary buffer and one Secondary buffer. The Spar-
tan-XL family has eight global low-skew buffers, two in each
corner. All can be sourced by either semi-dedicated pads
(GCK1-8) or internal nets.
Using the library symbol called BUFG results in the soft-
ware choosing the appropriate clock buffer, based on the
timing requirements of the design. A global buffer should be
specified for all timing-sensitive global signal distribution.
To use a global buffer, place a BUFGP (primary buffer),
BUFGS (secondary buffer), BUFGLS (Spartan-XL global
low-skew buffer), or BUFG (any buffer type) element in a
schematic or in HDL code.
Advanced Features Description
Distributed RAM
Optional modes for each CLB allow the function generators
(F-LUT and G-LUT) to be used as Random Access Mem-
ory (RAM).
Read and write operations are significantly faster for this
on-chip RAM than for off-chip implementations. This speed
advantage is due to the relatively short signal propagation
delays within the FPGA.
Memory Configuration Overview
There are two available memory configuration modes: sin-
gle-port RAM and dual-port RAM. For both these modes,
write operations are synchronous (edge-triggered), while
read operations are asynchronous. In the single-port mode,
a single CLB can be configured as either a 16 x 1, (16 x 1)
x 2, or 32 x 1 RAM array. In the dual-port mode, a single
CLB can be configured only as one 16 x 1 RAM array. The
different CLB memory configurations are summarized in
Table 8
. Any of these possibilities can be individually pro-
grammed into a Spartan/XL CLB.
The 16 x 1 single-port configuration contains a RAM
array with 16 locations, each one-bit wide. One 4-bit
address decoder determines the RAM location for write
and read operations. There is one input for writing data
and one output for reading data, all at the selected
address.
The (16 x 1) x 2 single-port configuration combines two
16 x 1 single-port configurations (each according to the
preceding description). There is one data input, one
data output and one address decoder for each array.
These arrays can be addressed independently.
The 32 x 1 single-port configuration contains a RAM
array with 32 locations, each one-bit wide. There is one
data input, one data output, and one 5-bit address
decoder.
The dual-port mode 16 x 1 configuration contains a
RAM array with 16 locations, each one-bit wide. There
are two 4-bit address decoders, one for each port. One
port consists of an input for writing and an output for
reading, all at a selected address. The other port
consists of one output for reading from an
independently selected address.
The appropriate choice of RAM configuration mode for a
given design should be based on timing and resource
requirements, desired functionality, and the simplicity of the
design process. Selection criteria include the following:
Whereas the 32 x 1 single-port, the (16 x 1) x 2 single-port,
and the 16 x 1 dual-port configurations each use one entire
CLB, the 16 x 1 single-port configuration uses only one half
of a CLB. Due to its simultaneous read/write capability, the
dual-port RAM can transfer twice as much data as the sin-
gle-port RAM, which permits only one data operation at any
given time.
CLB memory configuration options are selected by using
the appropriate library symbol in the design entry.
Single-Port Mode
There are three CLB memory configurations for the sin-
gle-port RAM: 16 x 1, (16 x 1) x 2, and 32 x 1, the functional
organization of which is shown in
Figure 12
.
The single-port RAM signals and the CLB signals (
Figure 2
on page 3
) from which they are originally derived are shown
in
Table 9
.
Table 8: CLB Memory Configurations
Mode
16 x 1
√
√
(16 x 1) x 2
√
32 x 1
√
Single-Port
Dual-Port
Table 9: Single-Port RAM Signals
RAM Signal
Function
Data In
Address
CLB Signal
DIN or H
1
F
1
-F
4
or G
1
-G
4
H
1
SR
K
F
OUT
or G
OUT
D
A[3:0]
A
4
(32 x 1 only) Address
WE
WCLK
SPO
Write Enable
Clock
Single Port Out
(Data Out)
Powered by ICminer.com Electronic-Library Service CopyRight 2003
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCS05XL-3CS280C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS280I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS84C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS84I | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3PC144C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05XL-3CS280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS84I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3PC100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。