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| 型號(hào)： | XCS05XL-3CS240I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列 |
| 文件頁數(shù)： | 54/66頁 |
| 文件大?。?/td> | 809K |
| 代理商： | XCS05XL-3CS240I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-54
DS060 (v1.5) March 2, 2000
TDI, TCK,
TMS
I
I/O
or I
(JTAG)
If boundary scan is used, these pins are Test Data In, Test Clock, and Test Mode Select
inputs respectively. They come directly from the pads, bypassing the IOBs. These pins
can also be used as inputs to the CLB logic after configuration is completed.
If the BSCAN symbol is not placed in the design, all boundary scan functions are inhib-
ited once configuration is completed, and these pins become user-programmable I/O.
In this case, they must be called out by special library elements. To use these pins,
place the library components TDI, TCK, and TMS instead of the usual pad symbols. In-
put or output buffers must still be used.
High During Configuration (HDC) is driven High until the I/O go active. It is available as
a control output indicating that configuration is not yet completed. After configuration,
HDC is a user-programmable I/O pin.
Low During Configuration (LDC) is driven Low until the I/O go active. It is available as a
control output indicating that configuration is not yet completed. After configuration, LDC
is a user-programmable I/O pin.
Before and during configuration, INIT is a bidirectional signal. A 1 k
- 10 k
external
pull-up resistor is recommended.
As an active Low open-drain output, INIT is held Low during the power stabilization and
internal clearing of the configuration memory. As an active Low input, it can be used
to hold the FPGA in the internal WAIT state before the start of configuration. Master
mode devices stay in a WAIT state an additional 30 to 300
μ
s after INIT has gone High.
During configuration, a Low on this output indicates that a configuration data error has
occurred. After the I/O go active, INIT is a user-programmable I/O pin.
Four Primary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. If not used to drive a global buffer, any of these pins is a user-pro-
grammable I/O.
The PGCK1-PGCK4 pins drive the four Primary Global Buffers. Any input pad symbol
connected directly to the input of a BUFGP symbol is automatically placed on one of
these pins.
Four Secondary Global inputs each drive a dedicated internal global net with short delay
and minimal skew. These internal global nets can also be driven from internal logic. If
not used to drive a global net, any of these pins is a user-programmable I/O pin.
The SGCK1-SGCK4 pins provide the shortest path to the four Secondary Global Buff-
ers. Any input pad symbol connected directly to the input of a BUFGS symbol is auto-
matically placed on one of these pins.
Eight Global inputs each drive a dedicated internal global net with short delay and min-
imal skew. These internal global nets can also be driven from internal logic. If not used
to drive a global net, any of these pins is a user-programmable I/O pin.
The GCK1-GCK8 pins provide the shortest path to the eight Global Low-Skew Buffers.
Any input pad symbol connected directly to the input of a BUFGLS symbol is automati-
cally placed on one of these pins.
During Express configuration, CS1 is used as a serial-enable signal for daisy-chaining.
HDC
O
I/O
LDC
O
I/O
INIT
I/O
I/O
PGCK1 -
PGCK4
(Spartan)
Weak
Pull-up
I or I/O
SGCK1 -
SGCK4
(Spartan)
Weak
Pull-up
I or I/O
GCK1 - GCK8
(Spartan-XL)
Weak
Pull-up
I or I/O
CS1
(Spartan-XL)
D0-D7
(Spartan-XL)
I
I/O
I
I/O
During Express configuration, these eight input pins receive configuration data. After
configuration, they are user-programmable I/O pins.
During Slave Serial or Master Serial configuration, DIN is the serial configuration data
input receiving data on the rising edge of CCLK. After configuration, DIN is a user-pro-
grammable I/O pin.
DIN
I
I/O
Table 18: Pin Descriptions (Continued)
Pin Name
I/O
During
Config.
I/O
After
Config.
Pin Description
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| XCS05XL-3CS256C | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCS05XL-3CS256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS256I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS280C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS280I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| XCS05XL-3CS84C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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