R
DS060 (v1.5) March 2, 2000
Powered by ICminer.com Electronic-Library Service CopyRight 2003
4-15
Spartan and Spartan-XL Families Field Programmable Gate Arrays
Initializing RAM at FPGA Configuration
Both RAM and ROM implementations in the Spartan/XL
families are initialized during device configuration. The ini-
tial contents are defined via an INIT attribute or property
attached to the RAM or ROM symbol, as described in the
schematic library guide. If not defined, all RAM contents
are initialized to zeros, by default.
RAM initialization occurs only during device configuration.
The RAM content is not affected by GSR.
More Information on using RAM inside CLBs
Three application notes are available from Xilinx that dis-
cuss synchronous (edge-triggered) RAM: "
Xilinx Edge-Trig-
gered and Dual-Port RAM Capability,
" "
Implementing
FIFOs in Xilinx RAM,
" and "
Synchronous and Asynchro-
nous FIFO Designs
." All three application notes apply to
both the Spartan and the Spartan-XL families.
Fast Carry Logic
Each CLB F-LUT and G-LUT contains dedicated arithmetic
logic for the fast generation of carry and borrow signals.
This extra output is passed on to the function generator in
the adjacent CLB. The carry chain is independent of normal
routing resources. (See
Figure 15
.)
Dedicated fast carry logic greatly increases the efficiency
and performance of adders, subtractors, accumulators,
comparators and counters. It also opens the door to many
new applications involving arithmetic operation, where the
previous generations of FPGAs were not fast enough or too
inefficient. High-speed address offset calculations in micro-
processor or graphics systems, and high-speed addition in
digital signal processing are two typical applications.
The two 4-input function generators can be configured as a
2-bit adder with built-in hidden carry that can be expanded
to any length. This dedicated carry circuitry is so fast and
efficient that conventional speed-up methods like carry
generate/propagate are meaningless even at the 16-bit
level, and of marginal benefit at the 32-bit level. This fast
carry logic is one of the more significant features of the
Spartan and Spartan-XL families, speeding up arithmetic
and counting functions.
The carry chain in 5V Spartan devices can run either up or
down. At the top and bottom of the columns where there
are no CLBs above and below, the carry is propagated to
the right. The default is always to propagate up the column,
as shown in the figures. The carry chain in Spartan-XL
devices can only run up the column, providing even higher
speed.
Figure 16 on page 16
shows a Spartan/XL CLB with dedi-
cated fast carry logic. The carry logic shares operand and
control inputs with the function generators. The carry out-
puts connect to the function generators, where they are
combined with the operands to form the sums.
Figure 17 on page 17
shows the details of the Spartan/XL
carry logic. This diagram shows the contents of the box
labeled "CARRY LOGIC" in
Figure 16
.
The fast carry logic can be accessed by placing special
library symbols, or by using Xilinx Relationally Placed Mac-
ros (RPMs) that already include these symbols.
X6610
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
CLB
Figure 15: Available Spartan/XL Carry Propagation
Paths