參數(shù)資料
型號： XCS05-3BG208C
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 36/66頁
文件大小： 809K
代理商： XCS05-3BG208C
R
Spartan and Spartan-XL Families Field Programmable Gate Arrays
4-36
DS060 (v1.5) March 2, 2000
Spartan DC Characteristics Over Operating Conditions
Note 1: With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
Note 2: With no output current loads, no active input pull-up resistors, all package pins at V
CC
or GND, and the FPGA configured with a
Tie option.
Spartan Global Buffer Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values where one global clock input
drives one vertical clock line in each accessible column,
and where all accessible IOB and CLB flip-flops are
clocked by the global clock net.
When fewer vertical clock lines are connected, the clock
distribution is faster; when multiple clock lines per column
are driven from the same global clock, the delay is longer.
For more specific, more precise, and worst-case guaran-
teed data, reflecting the actual routing structure, use the
values provided by the static timing analyzer (TRCE in the
Xilinx Development System) and back-annotated to the
simulation netlist. These path delays, provided as a guide-
line, have been extracted from the static timing analyzer
report. All timing parameters assume worst-case operating
conditions (supply voltage and junction temperature).
Symbol
V
OH
Description
Min
2.4
Max
Units
V
V
V
V
mA
mA
μ
A
pF
mA
mA
High-level output voltage @ I
OH
=
–
4.0 mA, V
CC
min
High-level output voltage @ I
OH
=
–
1.0 mA, V
CC
min
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min
(Note 1)
Quiescent FPGA supply current (Note 2)
TTL outputs
CMOS outputs
TTL outputs
CMOS outputs
Commercial
Industrial
V
CC
–
0.5
V
OL
0.4
0.4
3.0
6.0
+10
10
0.25
I
CCO
I
L
C
IN
I
RPU
I
RPD
Input or output leakage current
Input capacitance (sample tested)
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Pad pull-down (when selected) @ V
IN
= 5V (sample tested)
–
10
0.02
0.02
Speed Grade
Description
From pad through Primary buffer, to any clock K
-4
-3
Units
Symbol
T
PG
Device
XCS05
XCS10
XCS20
XCS30
XCS40
XCS05
XCS10
XCS20
XCS30
XCS40
Max
2.0
2.4
2.8
3.2
3.5
2.5
2.9
3.3
3.6
3.9
Max
4.0
4.3
5.4
5.8
6.4
4.4
4.7
5.8
6.2
6.7
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
From pad through Secondary buffer, to any clock K
T
SG
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