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This product has been discontinued. Please see
www.xilinx.com/partinfo/notify/pdn0007.htm
for details.
DS032 v1.1
Features
Industry's largest CPLD–960 macrocells
Industry's first SRAM-based CPLD
Multiple configuration modes
-
Master serial
-
Slave serial
-
Master parallel-up
-
Slave parallel
-
Synchronous peripheral
-
In-system configurable through JTAG port
Configuration times of under 1.0 second
IEEE 1149.1 compliant JTAG testing capability
-
5-pin JTAG interface
-
IEEE 1149.1 TAP controller
3.3V device
Innovative XPLA2 Architecture combines extreme
flexibility and high speeds
Eight synchronous clock networks with programmable
polarity at every macrocell
Up to 96 asynchronous clocks support complex
clocking needs
Innovative XOR structure at every macrocell provides
excellent logic reduction capability
Logic expandable to 36 product terms on a single
macrocell
PCI compliant
Advanced 0.35
μ
SRAM process
Design entry and verification using industry standard
and Xilinx CAE tools
Innovative Control Term structure provides either sum
terms of product terms in each logic block for:
-
3-state buffer control
-
Asynchronous macrocell register reset/preset
Global 3-state pin facilitates "bed of nails" testing
without sacrificing logic resources
Programmable slew rate control
Small form factor 492-pin PBGA package provides 384
I/O pins
Available in commercial and industrial temperature
ranges
Description
The XCR3960 device is a member of the CoolRunner
family of high-density SRAM-based CPLDs (Complex Pro-
grammable Logic Device) from Xilinx. This device com-
bines high-speed and deterministic pin-to-pin timing with
high density. The XCR3960 uses the patented Fast Zero
Power (FZP
) design technique that combines high speed
and low power for the first time ever in a CPLD. FZP allows
the XCR3960 to have true pin-to-pin timing delays of
7.5 ns, and standby currents of 100
μ
A without the need for
"turbo bits" or other power-down schemes. By replacing
conventional sense amplifier methods for implementing
product terms (a technique that has been used since the
bipolar era) with a cascaded chain of pure CMOS gates,
both standby and dynamic power are dramatically reduced
when compared to other CPLDs. The FZP design tech-
nique is also what allows Xilinx to offer a true CPLD archi-
tecture in a high-density device. Xilinx CoolRunner CPLDs
are approximately twice the density and yet consume only
half the power of standard CPLDs.
The Xilinx XCR3960 utilize the patented XPLA2 (eXtended
Programmable Logic Array) architecture. This architecture
combines the best features of both PAL- and PLA-type
logic structures to deliver high-speed and flexible logic allo-
cation that results in superior ability to make design
changes with fixed pinouts. The XPLA2 architecture is con-
structed from 80 macrocell Fast Modules that are con-
nected together by an interconnect array. Within each Fast
Module are four Logic Blocks of 20 macrocells each. Each
Logic Block contains a PAL structure with four dedicated
product terms for each macrocell. In addition, each Logic
Block has 32 additional product terms in a PLA structure
that can be shared through a fully programmable OR array
to any of the 20 macrocells. This combination efficiently
allocates logic throughout the Logic Block, which increases
device density and allows for design changes without rede-
fining the pinout or changing the system timing. The
XCR3960 offers pin-to-pin propagation delays of 7.5 ns
through the PAL array of a Fast Module; and if the PLA
array is used, an additional 1.5 ns is added to the delay, no
matter how many PLA product terms are used. If the inter-
connect array between Fast Modules is used, there is a
second fixed addition to the propagation delay of 4.0 ns.
This means that the worst case pin-to-pin propagation
delay within a fast module is 7.5 + 1.5 = 9.0 ns, and the
delay from any pin to any other pin across the entire chip is
7.5 + 4.0 = 11.5 ns if only the PAL array is used, and
7.5 + 1.5 + 4.0 = 13.0 ns if the PLA array is used. This
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XCR3960: 960 Macrocell SRAM
CPLD
DS032 (v1.3) October 9, 2000
0
8*
Product Specification
R
相關(guān)PDF資料 |
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| XCR5064C | 64 Macrocell CPLD with Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的64宏單元復(fù)雜可編程邏輯器件) |
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| XCR5064C-10PC44I | 64 Macrocell CPLD with Enhanced Clocking |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR-4 | 功能描述:XLR 連接器 ID RING YELLOW RoHS:否 制造商:Neutrik 標(biāo)準(zhǔn):Standard XLR 產(chǎn)品類型:Connectors 型式:Female 位置/觸點(diǎn)數(shù)量:3 端接類型:Solder 安裝風(fēng)格:Cable 方向:Vertical |
| XCR-5 | 功能描述:XLR 連接器 ID RING GREEN RoHS:否 制造商:Neutrik 標(biāo)準(zhǔn):Standard XLR 產(chǎn)品類型:Connectors 型式:Female 位置/觸點(diǎn)數(shù)量:3 端接類型:Solder 安裝風(fēng)格:Cable 方向:Vertical |
| XCR5032C-10PC44 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XCR5064 | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10PC44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD with Enhanced Clocking |
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