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參數(shù)資料
| 型號(hào)： | XCR5032C |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 32 Macrocell CPLD with Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的32宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 32宏單元CPLD增強(qiáng)型時(shí)鐘（帶增強(qiáng)時(shí)鐘控制的32個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 1/17頁 |
| 文件大?。?/td> | 329K |
| 代理商： | XCR5032C |
DS046 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
1
This product has been discontinued. Please see
for details.Features
Industry's first TotalCMOS PLD - both CMOS design
and process technologies
Fast Zero Power (FZP) design technique provides
ultra-low power and very high speed
High speed pin-to-pin delays of 6 ns
Ultra-low static power of less than 75
μ
A
100% routable with 100% utilization while all pins and
all macrocells are fixed
Deterministic timing model that is extremely simple to
use
Up to six clocks available
Programmable clock polarity at every macrocell
5V, In-System Programmable (ISP) using a JTAG
interface
-
On-chip supervoltage generation
-
ISP commands include: Enable, Erase, Program,
Verify
-
Supported by multiple ISP programming platforms
-
Four pin JTAG interface (TCK, TMS, TDI, TDO)
-
JTAG commands include: Bypass, Idcode
Support for complex asynchronous clocking
Innovative XPLA
architecture combines high speed
with extreme flexibility
1000 erase/program cycles guaranteed
20 years data retention guaranteed
Logic expandable to 37 product terms
PCI compliant
Advanced 0.5
μ
E
2
CMOS process
Security bit prevents unauthorized access
Design entry and verification using industry standard
and Xilinx CAE tools
Reprogrammable using industry standard device
programmers
Innovative Control Term structure provides either sum
terms or product terms in each logic block for:
-
Programmable 3-state buffer
-
Asynchronous macrocell register preset/reset
-
Up to two asynchronous clocks
Programmable global 3-state pin facilitates `bed of
nails' testing without using logic resources
Available in both PLCC and VQFP packages
Description
The XCR5032C CPLD (Complex Programmable Logic
Device) is a member of the CoolRunner
family of CPLDs
from Xilinx. These devices combine high speed and zero
power in a 32 macrocell CPLD. With the FZP design tech-
nique, the XCR5032C offers true pin-to-pin speeds of 6 ns,
while simultaneously delivering power that is less than
75
μ
A at standby without the need for "turbo bits" or other
power down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era)
with a cascaded chain of pure CMOS gates, the dynamic
power is also substantially lower than any competing
CPLD. These devices are the first TotalCMOS PLDs, as
they use both a CMOS process technology
and
the pat-
ented full CMOS FZP design technique. For 3V applica-
tions, Xilinx also offers the high speed XCR3032C CPLD
that offers pin-to-pin speeds of 8 ns.
The Xilinx FZP CPLDs utilize the patented XPLA (extended
Programmable Logic Array) architecture. The XPLA archi-
tecture combines the best features of both PLA and PAL
type structures to deliver high speed and flexible logic allo-
cation that results in superior ability to make design
changes with fixed pinouts. The XPLA structure in each
logic block provides a fast 6 ns PAL path with five dedicated
product terms per output. This PAL path is joined by an
additional PLA structure that deploys a pool of 32 product
terms to a fully programmable OR array that can allocate
the PLA product terms to any output in the logic block. This
combination allows logic to be allocated efficiently through-
out the logic block and supports as many as 37 product
terms on an output. The speed with which logic is allocated
from the PLA array to an output is only 2 ns, regardless of
the number of PLA product terms used, which results in
worst case t
PD
’
s of only 8 ns from any pin to any other pin.
In addition, logic that is common to multiple outputs can be
placed on a single PLA product term and shared across
multiple outputs via the OR array, effectively increasing
design density.
The XCR5032C CPLDs are supported by industry standard
CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, Synario, Viewlogic, and Synplicity), using text
(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-
ification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms. Device fitting
uses Xilinx developed tools including WebFITTER.
0
XCR5032C: 32 Macrocell CPLD
with Enhanced Clocking
DS046 (v1.3) October 9, 2000
0
14*
Product Specification
相關(guān)PDF資料 |
PDF描述 |
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| XCR5064C | 64 Macrocell CPLD with Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的64宏單元復(fù)雜可編程邏輯器件) |
| XCR5064 | 64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10PC44C | 64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10PC44I | 64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10VQ100C | 64 Macrocell CPLD with Enhanced Clocking |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| XCR5032C-10PC44 | 制造商: 功能描述: 制造商:undefined 功能描述: |
| XCR5064 | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10PC44C | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10PC44I | 制造商:XILINX 制造商全稱:XILINX 功能描述:64 Macrocell CPLD with Enhanced Clocking |
| XCR5064C-10VQ100C | 制造商:Xilinx 功能描述:COMPLEX-EEPLD, 64-CELL, 12NS PROP DELAY, 100 Pin, Plastic, TQFP |
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