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參數(shù)資料
| 型號(hào)： | XCR3256XLSERIES |
| 英文描述： | 256 Macrocell CPLD |
| 中文描述： | 256個(gè)宏單元CPLD |
| 文件頁(yè)數(shù)： | 3/12頁(yè) |
| 文件大?。?/td> | 113K |
| 代理商： | XCR3256XLSERIES |
XCR3256XL 256 Macrocell CPLD
DS013 (v1.9) January 8, 2002
Preliminary Product Specification
1-800-255-77783
R
AC Electrical Characteristics Over Recommended Operating Conditions
(1,2)
Symbol
Parameter
-7
-10
-12
Unit
Min.
Max.
Min.
Max.
Min.
Max.
T
PD1
T
PD2
T
CO
T
SUF
T
SU1(4)
T
SU2
T
H(4)
T
WLH(4)
Tt
PLH(4)
T
R(4)
T
L(4)
f
SYSTEM(4)
T
CONFIG(4)
T
INIT(4)
T
POE(4)
T
POD(4)
T
PCO(4)
T
PAO(4)
Notes:
1.
Specifications measured with one output switching.
2.
See XPLA3 family data sheet (
DS012
) for recommended operating conditions.
3.
See
Figure 4
for derating.
4.
These parameters guaranteed by design and/or characterization, not testing.
5.
Typical current draw during configuration is 10 mA at 3.6V.
6.
Output C
L
= 5 pF.
Propagation delay time (single p-term)
Propagation delay time (OR array)
(3)
-
7.0
-
9.0
-
10.8
ns
-
7.5
-
10.0
-
12.0
ns
Clock to output (global synchronous pin clock)
-
4.5
-
5.8
-
6.9
ns
Setup time (fast input register)
2.5
-
3.0
-
3.0
-
ns
Setup time (single p-term)
4.3
-
5.5
-
6.7
-
ns
Setup time (OR array)
4.8
-
6.5
-
7.9
-
ns
Hold time
0
-
0
-
0
-
ns
Global Clock pulse width (High or Low)
3.0
-
4.0
-
5.0
-
ns
P-term clock pulse width
4.5
-
6.0
-
7.5
-
ns
Input rise time
-
20
-
20
-
20
ns
Input fall time
-
20
-
20
-
20
ns
Maximum system frequency
Configuration time
(5)
-
140
-
105
-
88
MHz
-
120
-
120
-
120
μ
s
μ
s
ns
ISP initialization time
-
120
-
120
-
120
P-term OE to output enabled
P-term OE to output disabled
(6)
-
9.0
-
11.0
-
13.0
-
9.0
-
11.0
-
13.0
ns
P-term clock to output
-
8.0
-
10.3
-
12.4
ns
P-term set/reset to output valid
-
9.0
-
11.0
-
13.0
ns
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