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參數(shù)資料
| 型號： | XCR3128A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 128 Macrocell CPLD with Enhanced Clocking(帶增強(qiáng)時(shí)鐘控制的128宏單元復(fù)雜可編程邏輯器件) |
| 中文描述： | 128個(gè)宏單元CPLD增強(qiáng)型時(shí)鐘（帶增強(qiáng)時(shí)鐘控制的128個(gè)宏單元復(fù)雜可編程邏輯器件） |
| 文件頁數(shù)： | 8/18頁 |
| 文件大小： | 157K |
| 代理商： | XCR3128A |
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
8
This product has been discontinued. Please see
for details.3.3V, In-System Programming (ISP)
ISP is the ability to reconfigure the logic and functionality of
a device, printed circuit board, or complete electronic sys-
tem before, during, and after its manufacture and shipment
to the end customer. ISP provides substantial benefits in
each of the following areas:
Design
-
Faster time-to-market
-
Debug partitioning and simplified prototyping
-
Printed circuit board reconfiguration during debug
-
Better device and board level testing
Manufacturing
-
Multi-functional hardware
-
Reconfigurability for test
-
Eliminates handling of "fine lead-pitch" components
for programming
-
Reduced inventory and manufacturing costs
-
Field Support
-
Easy remote upgrades and repair
-
Support for field configuration, reconfiguration, and
customization
Improved quality and reliability
The Xilinx XCR3128A allows for 3.3V in-system program-
ming/reprogramming of its EEPROM cells via its JTAG
interface. An on-chip charge pump eliminates the need for
externally provided supervoltages, so that the XCR3128A
may be easily programmed on the circuit board using only
the 3V supply required by the device for normal operation.
A set of low-level ISP basic commands implemented in the
XCR3128A enable this feature. The ISP commands imple-
mented in the Xilinx XCR3128A are specified in
Table 5
.
Please note that an ENABLE command must precede all
ISP commands
unless
an ENABLE command has already
been given for a preceding ISP command.
Table 3: JTAG Pin Description
Pin
TCK
Name
Description
Test Clock Output
Clock pin to shift the serial data and instructions in and out of the TDI and TDO pins,
respectively.
Serial input pin selects the JTAG instruction mode. TMS should be driven High
during user mode operation.
Serial input pin for instructions and test data. Data is shifted in on the rising edge of
TCK.
Serial output pin for instructions and test data. Data is shifted out on the falling edge
of TCK. The signal is 3-stated if data is not being shifted out of the device.
TMS
Test Mode Select
TDI
Test Data Input
TDO
Test Data Output
Table 4: XCR3128A JTAG Pinout by Package Type
Device
XCR3128A
100-pin VQFP
128-pin TQFP
(Pin Number / Macrocell #)
TMS
15/C15
21/C15
TCK
62/F15
82/F15
TDI
4/B15
8/B15
TDO
73/G15
95/G15
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3128XL-10VQ100C | XCR3128XL 128 Macrocell CPLD |
| XCR3128XL-10VQ100I | T1/E1 Transformer |
| XCR3128XL-6VQ100I | XCR3128XL 128 Macrocell CPLD |
| XCR3128XL-7VQ100C | XCR3128XL 128 Macrocell CPLD |
| XCR3128XL-7VQ100I | XCR3128XL 128 Macrocell CPLD |
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|---|---|
| XCR3128A-10TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-10TQ128I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-10VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-10VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
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