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參數(shù)資料
| 型號： | XCR3128A |
| 廠商： | Xilinx, Inc. |
| 英文描述： | 128 Macrocell CPLD with Enhanced Clocking(帶增強時鐘控制的128宏單元復雜可編程邏輯器件) |
| 中文描述： | 128個宏單元CPLD增強型時鐘（帶增強時鐘控制的128個宏單元復雜可編程邏輯器件） |
| 文件頁數(shù)： | 6/18頁 |
| 文件大?。?/td> | 157K |
| 代理商： | XCR3128A |
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
DS035 (v1.3) October 9, 2000
www.xilinx.com
1-800-255-7778
6
This product has been discontinued. Please see
for details.TotalCMOS Design Technique for Fast Zero
Power
Xilinx is the first to offer a TotalCMOS CPLD, both in pro-
cess technology and design technique. Xilinx employs a
cascade of CMOS gates to implement its Sum of Products
instead of the traditional sense amp approach. This CMOS
gate implementation allows Xilinx to offer CPLDs which are
both high-performance and low power, breaking the para-
digm that to have low power, you must have low perfor-
mance. Refer to
Figure 5
and
Table 1
showing the I
CC
vs.
Frequency of the XCR3128A TotalCMOS CPLD (data
taken with eight up/down, loadable 16-bit counters at 3.3V,
25
°
C).
Figure 5: I
CC
vs. Frequency @ V
CC
= 3.3V, 25
°
C
Table 1: I
CC
vs. Frequency
(V
CC
= 3.3V, 25
°
C)
Frequency (MHz)
Typical I
CC
(mA)
0
1
20
12.7
40
25.5
60
38.1
80
50.5
100
62.8
120
74.7
0.03
0.7
FREQUENCY (MHz)
SP00617
1
20
40
60
80
100
0
10
20
30
40
60
I
(mA)
50
120
70
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| XCR3128XL-10VQ100C | XCR3128XL 128 Macrocell CPLD |
| XCR3128XL-10VQ100I | T1/E1 Transformer |
| XCR3128XL-6VQ100I | XCR3128XL 128 Macrocell CPLD |
| XCR3128XL-7VQ100C | XCR3128XL 128 Macrocell CPLD |
| XCR3128XL-7VQ100I | XCR3128XL 128 Macrocell CPLD |
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| XCR3128A-10TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-10TQ128I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-10VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-10VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
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