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參數(shù)資料
| 型號(hào)： | XCR3128A-10VQ100C |
| 廠(chǎng)商： | XILINX INC |
| 元件分類(lèi)： | PLD |
| 英文描述： | CPLD with Enhanced Clocking |
| 中文描述： | EE PLD, 10 ns, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁(yè)數(shù)： | 9/17頁(yè) |
| 文件大小： | 268K |
| 代理商： | XCR3128A-10VQ100C |
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Terminations
The CoolRunner XCR3128A CPLDs are TotalCMOS
devices. As with other CMOS devices, it is important to
consider how to properly terminate unused inputs and I/O
pins when fabricating a PC board. Allowing unused inputs
and I/O pins to float can cause the voltage to be in the linear
region of the CMOS input structures, which can increase
the power consumption of the device. The XCR3128A
CPLDs have programmable on-chip pull-down resistors on
each I/O pin. These pull-downs are automatically activated
by the fitter software for all unused I/O pins. Note that an I/O
macrocell used as buried logic that does not have the I/O
pin used for input is considered to be unused, and the
pull-down resistors will be turned on. We recommend that
any unused I/O pins on the XCR3128A device be left
unconnected.
There are no on-chip pull-down structures associated with
the dedicated input pins. Xilinx recommends that any
unused dedicated inputs be terminated with external 10k
pull-up resistors. These pins can be directly connected to
V
CC
or GND, but using the external pull-up resistors main-
tains maximum design flexibility should one of the unused
dedicated inputs be needed due to future design changes.
When using the JTAG/ISP functions, it is also recom-
mended that 10k
pull-up resistors be used on each of the
pins associated with the four mandatory JTAG signals. Let-
ting these signals float can cause the voltage on TMS to
come close to ground, which could cause the device to
enter JTAG/ISP mode at unspecified times. See the appli-
cation notes
JTAG and ISP Overview for Xilinx XPLA1 and
XPLA2 CPLDs
and
Terminating Unused I/O Pins in Xilinx
XPLA1 and XPLA2 CoolRunner
CPLDs
for more informa-
tion.
Table 5: Low Level ISP Commands
Instruction
(Register Used)
Enable
(ISP Shift Register)
Erase
(ISP Shift Register)
Program
(ISP Shift Register)
Verify
(ISP Shift Register)
Instruction Code
Description
1001
Enables the Erase, Program, and Verify commands.
1010
Erases the entire EEPROM array.
1011
Programs the data in the ISP Shift Register into the addressed
EEPROM row.
Transfers the data from the addressed row to the ISP Shift
Register. .
1100
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3128A-10VQ100I | CPLD with Enhanced Clocking |
| XCR3128A-10TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-10TQ128I | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | CPLD with Enhanced Clocking |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128A-10VQ100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100C | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100I | 制造商:XILINX 制造商全稱(chēng):XILINX 功能描述:CPLD with Enhanced Clocking |
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