- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄375011 > XCR3128A-10VQ100C (XILINX INC) CPLD with Enhanced Clocking PDF資料下載
參數(shù)資料
| 型號： | XCR3128A-10VQ100C |
| 廠商： | XILINX INC |
| 元件分類： | PLD |
| 英文描述： | CPLD with Enhanced Clocking |
| 中文描述： | EE PLD, 10 ns, PQFP100 |
| 封裝： | PLASTIC, VQFP-100 |
| 文件頁數(shù)： | 7/17頁 |
| 文件大?。?/td> | 268K |
| 代理商： | XCR3128A-10VQ100C |
R
XCR3128A: 128 Macrocell CPLD with Enhanced Clocking
7
www.xilinx.com
1-800-255-7778
DS035 (v1.2) August 10, 2000
JTAG Testing Capability
JTAG
Boundary-scan Test (BST) feature defined for integrated
circuits by IEEE Standard 1149.1. This standard defines
input/output pins, logic control functions, and commands
which facilitate both board and device level testing without
the use of specialized test equipment. The Xilinx
XCR3128A devices use the JTAG Interface for In-System
Programming/Reprogramming. Although only a subset of
the full JTAG command set is implemented (see
),the
commonly-used
acronym
for
the
The Xilinx XCR3128A
’
s JTAG interface includes a TAP Port
defined by the IEEE 1149.1 JTAG Specification. As imple-
mented in the Xilinx XCR3128A, the TAP Port includes four
of the five pins (refer to
Table 3
) described in the JTAG
specification: TCK, TMS, TDI, and TDO. The fifth signal
defined by the JTAG specification is TRST* (Test Reset).
TRST* is considered an optional signal, since it is not actu-
ally required to perform BST or ISP. The Xilinx XCR3128A
saves an I/O pin for general purpose use by not implement-
ing the optional TRST* signal in the JTAG interface.
Instead, the Xilinx XCR3128A supports the test reset func-
tionality through the use of its power-up reset circuit, which
is included in all Xilinx CPLDs. The pins associated with the
TAP Port should connect to an external pull-up resistor to
keep the JTAG signals from floating when they are not
being used. In the Xilinx XCR3128A, the four mandatory
JTAG pins each require a unique, dedicated pin on the
device. The devices come from the factory with these I/O
pins set to perform JTAG functions, but through the soft-
ware, the final function of these pins can be controlled. If
the end application will require the device to be repro-
grammed at some future time with ISP, then the pins can be
left as dedicated JTAG functions, which means they are not
available for use as general purpose I/O pins. However,
unlike competing CPLDs, the Xilinx XCR3128A allow the
macrocells associated with these pins to be used as buried
logic when the JTAG/ISP function is enabled. This is the
default state for the software, and no action is required to
leave these pins enabled for the JTAG/ISP functions. If,
however, JTAG/ISP is not required in the end application,
the software can specify that this function be turned off and
that these pins be used as general purpose I/O. Because
the devices initially have the JTAG/ISP functions enabled,
the JEDEC file can be downloaded into the device once,
after which the JTAG/ISP pins will become general purpose
I/O. This feature is good for manufacturing because the
devices can be programmed during test and assembly of
the end product and yet still use all of the I/O pins after the
programming is done. It eliminates the need for a costly,
separate programming step in the manufacturing process.
Of course, if the JTAG/ISP function is never required, this
feature can be turned off in the software and the device can
be programmed with an industry-standard programmer,
leaving the pins available for I/O functions.
Table 4
defines
the dedicated pins used by the four mandatory JTAG sig-
nals for each of the XCR3128A package types.
Table 2: XCR3128A Low-level JTAG Boundary-scan Commands
Instruction
(Instruction Code)
Register Used
Bypass
(1111)
Bypass Register
Description
Places the 1-bit bypass register between the TDI and TDO pins, which allows the BST
data to pass synchronously through the selected device to adjacent devices during
normal device operation. The Bypass instruction can be entered by holding TDI at a
constant high value and completing an Instruction-scan cycle.
Selects the IDCODE register and places it between TDI and TDO, allowing the
IDCODE to be serially shifted out of TDO. The IDCODE instruction permits blind
interrogation of the components assembled onto a printed circuit board. Thus, in
circumstances where the component population may vary, it is possible to determine
what components exist in a product.
Idcode
(0001)
Boundary-scan Register
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| XCR3128A-10VQ100I | CPLD with Enhanced Clocking |
| XCR3128A-10TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-10TQ128I | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | CPLD with Enhanced Clocking |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XCR3128A-10VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12TQ128I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100C | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
| XCR3128A-12VQ100I | 制造商:XILINX 制造商全稱:XILINX 功能描述:CPLD with Enhanced Clocking |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。