Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
39
Configuration Switching Characteristics
Table 40: Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Power-up Timing Characteristics
Program Latency
ms, Max
Power-on-Reset
50
ms, Max
TICCK
CCLK (output) delay
ns, Min
TPROGRAM
Program Pulse Width
250
ns, Min
Master/Slave Serial Mode Programming Switching
TDCCK/TCCKD
DIN Setup/Hold, slave mode
5.0/0.0
ns, Min
TDSCCK/TSCCKD
DIN Setup/Hold, master mode
5.0/0.0
ns, Min
TCCO
DOUT at 3.3V
ns, Max
DOUT at 2.5V
ns, Max
DOUT at 1.8V
ns, Max
FMCCK
Maximum Frequency, master mode with respect to
nominal CCLK.
100
MHz,
Max
FMCCKTOL
Frequency Tolerance, master mode with respect to
nominal CCLK.
±55
%
FMSCCK
Slave mode external CCLK
100
MHz
SelectMAP Mode Programming Switching
TSMDCCK/TSMCCKD
SelectMAP Data Setup/Hold
5.0/0.0
ns, Min
TSMCSCCK/TSMCCKCS
CSI_B Setup/Hold
ns, Min
TSMCCKW/TSMWCCK
RDWR_B Setup/Hold
ns, Min
TSMCKCSO
CSO_B clock to out
(330
pull-up resistor required)
ns, Max
TSMCO
CCLK to DATA out in readback at 3.3V
ns, Max
CCLK to DATA out in readback at 2.5V
ns, Max
CCLK to DATA out in readback at 1.8V
ns, Max
FSMCCK
Maximum Frequency with respect to nominal CCLK.
100
MHz, Max
FRBCCK
Maximum Readback Frequency with respect to
nominal CCLK
70
MHz, Max
FMCCKTOL
Frequency Tolerance with respect to nominal CCLK.
±55
%
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP
TMS and TDI Setup time before TCK/ Hold time after
TCK
ns, Min
TTCKTDO
TCK falling edge to TDO output valid at 3.3V
ns, Max
TCK falling edge to TDO output valid at 2.5V
ns, Max
TCK falling edge to TDO output valid at 1.8V
ns, Max
FTCK
Maximum configuration TCK clock frequency
20
MHz, Max
FTCKB
Maximum boundary-scan TCK clock frequency
20
MHz, Max