參數(shù)資料
型號： XC7K420T-1FFG1156E
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, PBGA1156
封裝： LEAD FREE, FBGA-1156
文件頁數(shù)： 19/50頁
文件大?。?/td> 1218K
代理商： XC7K420T-1FFG1156E
Kintex-7 FPGAs Data Sheet: DC and Switching Characteristics
DS182 (v1.1) April 1, 2011
Advance Product Specification
26
Input/Output Logic Switching Characteristics
HSTL (High-Speed Transceiver Logic), Class I & II, with DCI HSTL_I_DCI, HSTL_II_DCI
50
0
VREF
0.75
HSTL, Class I & II, 1.8V, with DCI
HSTL_I_DCI_18, HSTL_II_DCI_18
50
0
VREF
0.9
SSTL (Stub Series Termi.Logic), Class I & II, 1.8V, with DCI SSTL18_I_DCI, SSTL18_II_DCI
50
0
VREF
0.9
SSTL15, with DCI
SSTL15_DCI
50
0
VREF
0.675
SSTL135, with DCI
SSTL135_DCI
50
0
VREF
0.75
Notes:
1.
CREF is the capacitance of the probe, nominally 0 pF.
2.
The value given is the differential output voltage.
Table 30: ILOGIC Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-2
-1
-1L
Setup/Hold
TICE1CK/TICKCE1
CE1 pin Setup/Hold with respect to CLK
0.31/
0.05
0.36/
0.06
0.44/
0.07
ns
TISRCK/TICKSR
SR pin Setup/Hold with respect to CLK
1.00/
–0.14
1.15/
–0.14
1.39/
–0.14
ns
TIDOCKE2/TIOCKDE2
D pin Setup/Hold with respect to CLK without Delay
(HP I/O banks only)
0.11/
0.38
0.13/
0.42
0.15/
0.49
ns
TIDOCKDE2/TIOCKDDE2 DDLY pin Setup/Hold with respect to CLK (using IDELAY)
(HP I/O banks only)
0.14/
0.29
0.17/
0.32
0.20/
0.37
ns
TIDOCKE3/TIOCKDE3
D pin Setup/Hold with respect to CLK without Delay
(HR I/O banks only)
0.11/
0.38
0.13/
0.42
0.15/
0.49
ns
TIDOCKDE3/TIOCKDDE3 DDLY pin Setup/Hold with respect to CLK (using IDELAY)
(HR I/O banks only)
0.14/
0.29
0.17/
0.32
0.20/
0.37
ns
Combinatorial
TIDIE2
D pin to O pin propagation delay, no Delay
(HP I/O banks only)
0.19
0.21
0.24
ns
TIDIDE2
DDLY pin to O pin propagation delay (using IDELAY)
(HP I/O banks only)
0.22
0.24
0.28
ns
TIDIE3
D pin to O pin propagation delay, no Delay
(HR I/O banks only)
0.19
0.21
0.24
ns
TIDIDE3
DDLY pin to O pin propagation delay (using IDELAY)
(HR I/O banks only)
0.22
0.24
0.28
ns
Sequential Delays
TIDLOE2
D pin to Q1 pin using flip-flop as a latch without Delay
(HP I/O banks only)
0.48
0.54
0.62
ns
TIDLODE2
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HP I/O banks only)
0.51
0.57
0.66
ns
TIDLOE3
D pin to Q1 pin using flip-flop as a latch without Delay
(HR I/O banks only)
0.48
0.54
0.62
ns
TIDLODE3
DDLY pin to Q1 pin using flip-flop as a latch (using IDELAY)
(HR I/O banks only)
0.51
0.57
0.66
ns
TICKQ
CLK to Q outputs
0.55
0.61
0.70
ns
Table 29: Output Delay Measurement Methodology (Cont’d)
Description
I/O Standard
Attribute
RREF
(
)
CREF(1)
(pF)
VMEAS
(V)
VREF
(V)
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