參數(shù)資料
型號(hào): XC6VCX240T-2FFG1156I
廠商: Xilinx Inc
文件頁數(shù): 40/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 241K 1156FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 18840
邏輯元件/單元數(shù): 241152
RAM 位總計(jì): 15335424
輸入/輸出數(shù): 600
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
45
MMCM Switching Characteristics
Table 55: Regional Clock Switching Characteristics (BUFR)
Symbol
Description
Speed Grade
Units
-2
-1
TBRCKO_O
Clock to out delay from I to O
0.75
ns
0.75
ns
0.75
ns
0.75
ns
TBRCKO_O_BYP
Clock to out delay from I to O with Divide Bypass attribute set
0.37
ns
0.37
ns
0.37
ns
0.37
ns
TBRDO_O
Propagation delay from CLR to O
0.83
ns
Maximum Frequency
FMAX
Regional clock tree (BUFR)
300
MHz
Table 56: Horizontal Clock Buffer Switching Characteristics (BUFH)
Symbol
Description
Speed Grade
Units
-2
-1
TBHCKO_O
BUFH delay from I to O
0.13
ns
TBHCCK_CE/TBHCKC_CE
CE pin Setup and Hold
0.05/0.05
ns
Maximum Frequency
FMAX
Horizontal clock buffer (BUFH)
700
MHz
Table 57: MMCM Specification
Symbol
Description
Speed Grade
Units
-2
-1
FINMAX
Maximum Input Clock Frequency(1)
700
MHz
FINMIN
Minimum Input Clock Frequency
10
MHz
FINJITTER
Maximum Input Clock Period Jitter
< 20% of clock input period or 1 ns
Max
FINDUTY
Allowable Input Duty Cycle: 10—49 MHz
25/75
%
Allowable Input Duty Cycle: 50—199 MHz
30/70
%
Allowable Input Duty Cycle: 200—399 MHz
35/65
%
Allowable Input Duty Cycle: 400—499 MHz
40/60
%
Allowable Input Duty Cycle: >500 MHz
45/55
%
FMIN_PSCLK
Minimum Dynamic Phase Shift Clock Frequency
0.01
MHz
FMAX_PSCLK
Maximum Dynamic Phase Shift Clock Frequency
450
MHz
FVCOMIN
Minimum MMCM VCO Frequency
600
MHz
FVCOMAX
Maximum MMCM VCO Frequency
1200
MHz
FBANDWIDTH
Low MMCM Bandwidth at Typical(2)
1.00
MHz
High MMCM Bandwidth at Typical(2)
4.00
MHz
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