參數(shù)資料
型號(hào): XC6VCX240T-2FFG1156I
廠商: Xilinx Inc
文件頁數(shù): 17/52頁
文件大?。?/td> 0K
描述: IC FPGA VIRTEX 6 241K 1156FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 18840
邏輯元件/單元數(shù): 241152
RAM 位總計(jì): 15335424
輸入/輸出數(shù): 600
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 1156-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 1156-FCBGA(35x35)
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
24
Performance Characteristics
This section provides the performance characteristics of some common functions and designs implemented in Virtex-6 CXT
devices. The numbers reported here are worst-case values; they have all been fully characterized. These values are subject
to the same guidelines as the Switching Characteristics, page 25.
Table 35: Interface Performances
Description
Speed Grade
-2
-1
Networking Applications
SDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 8)
650 Mb/s
625 Mb/s
DDR LVDS transmitter (using OSERDES; DATA_WIDTH = 4 to 10)
1.25 Gb/s
1.0 Gb/s
SDR LVDS receiver (SFI-4.1)(1)
650 Mb/s
625 Mb/s
DDR LVDS receiver (SFI-4.2)(1)
1.0 Gb/s
0.9 Gb/s
Maximum Physical Interface (PHY) Rate for Memory Interfaces(2)(3)
DDR2
666 Mb/s
DDR3
800 Mb/s
666 Mb/s
QDR II + SRAM
250 MHz
Notes:
1.
LVDS receivers are typically bounded with certain applications where specific DPA algorithms dominate deterministic performance.
2.
Based on Xilinx memory characterization platforms designed according to the guidelines in the Virtex-6 FPGA Memory Interface Solutions
User Guide.
3.
Consult the Virtex-6 FPGA Memory Interface Solutions Data Sheet for performance and feature information on memory interface cores
(controller plus PHY).
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