參數(shù)資料
型號(hào): XC6VCX240T-1FFG784C
廠商: Xilinx Inc
文件頁(yè)數(shù): 27/52頁(yè)
文件大小: 0K
描述: IC FPGA VIRTEX 6 241K 784FFGBGA
產(chǎn)品培訓(xùn)模塊: Virtex-6 FPGA Overview
產(chǎn)品變化通告: Virtex-6 FIFO Input Logic Reset 18/Apr/2011
標(biāo)準(zhǔn)包裝: 1
系列: Virtex® 6 CXT
LAB/CLB數(shù): 18840
邏輯元件/單元數(shù): 241152
RAM 位總計(jì): 15335424
輸入/輸出數(shù): 400
電源電壓: 0.95 V ~ 1.05 V
安裝類(lèi)型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 784-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 784-FCBGA
Virtex-6 CXT Family Data Sheet
DS153 (v1.6) February 11, 2011
Product Specification
33
Output Serializer/Deserializer Switching Characteristics
Table 45: OSERDES Switching Characteristics
Symbol
Description
Speed Grade
Units
-2
-1
Setup/Hold
TOSDCK_D/TOSCKD_D
D input Setup/Hold with respect to CLKDIV
0.31/–0.12
ns
TOSDCK_T/TOSCKD_T(1)
T input Setup/Hold with respect to CLK
0.56/–0.08
ns
TOSDCK_T2/TOSCKD_T2(1)
T input Setup/Hold with respect to CLKDIV
0.31/–0.08
ns
TOSCCK_OCE/TOSCKC_OCE
OCE input Setup/Hold with respect to CLK
0.22/–0.05
ns
TOSCCK_S
SR (Reset) input Setup with respect to CLKDIV
0.07
ns
TOSCCK_TCE/TOSCKC_TCE
TCE input Setup/Hold with respect to CLK
0.21/–0.05
ns
Sequential Delays
TOSCKO_OQ
Clock to out from CLK to OQ
0.82
ns
TOSCKO_TQ
Clock to out from CLK to TQ
0.82
ns
Combinatorial
TOSDO_TTQ
T input to TQ Out
0.97
ns
Notes:
1.
TOSDCK_T2 and TOSCKD_T2 are reported as TOSDCK_T/TOSCKD_T in the TRACE report.
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XC6VCX240T-1FFG784I 功能描述:IC FPGA VIRTEX 6 241K 784FFGBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA(現(xiàn)場(chǎng)可編程門(mén)陣列) 系列:Virtex® 6 CXT 產(chǎn)品變化通告:Step Intro and Pkg Change 11/March/2008 標(biāo)準(zhǔn)包裝:1 系列:Virtex®-5 SXT LAB/CLB數(shù):4080 邏輯元件/單元數(shù):52224 RAM 位總計(jì):4866048 輸入/輸出數(shù):480 門(mén)數(shù):- 電源電壓:0.95 V ~ 1.05 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:1136-BBGA,F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:1136-FCBGA 配用:568-5088-ND - BOARD DEMO DAC1408D750122-1796-ND - EVALUATION PLATFORM VIRTEX-5
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