參數(shù)資料
型號： XC6SLX150T-2FG900I
廠商： Xilinx Inc
文件頁數(shù)： 61/89頁
文件大?。?/td> 0K
描述： IC FPGA SPARTAN 6 900FGGBGA
標(biāo)準(zhǔn)包裝： 27
系列： Spartan® 6 LXT
LAB/CLB數(shù)： 11519
邏輯元件/單元數(shù)： 147443
RAM 位總計： 4939776
輸入/輸出數(shù)： 540
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 900-BBGA
供應(yīng)商設(shè)備封裝： 900-FBGA
Spartan-6 FPGA Data Sheet: DC and Switching Characteristics
DS162 (v3.0) October 17, 2011
Product Specification
64
Table 59: Switching Characteristics for the Phase-Shift Clock in Variable Phase Mode(1)
Symbol
Description
Amount of Phase Shift
Units
Phase Shifting Range
When CLKIN < 60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
±(INTEGER(10 x (TCLKIN – 3 ns)))
steps
When CLKIN
60 MHz, the maximum allowed
number of DCM_DELAY_STEP steps for a
given CLKIN clock period, where T = CLKIN
clock period in ns. When using
CLKIN_DIVIDE_BY_2 = TRUE, double the
clock-effective clock period.
±(INTEGER(15 x (TCLKIN – 3 ns)))
steps
FINE_SHIFT_RANGE_MIN
Minimum guaranteed delay for variable phase
shifting.
±(MAX_STEPS x DCM_DELAY_STEP_MIN)
ps
FINE_SHIFT_RANGE_MAX
Maximum guaranteed delay for variable phase
shifting
±(MAX_STEPS x DCM_DELAY_STEP_MAX)
ps
Notes:
1.
The values in this table are based on the operating conditions described in Table 53 and Table 58.
2.
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM has no initial fixed-phase shifting, that is, the PHASE_SHIFT
attribute is set to 0.
3.
The DCM_DELAY_STEP values are provided at the end of Table 54.
Table 60: Miscellaneous DCM Timing Parameters(1)
Symbol
Description
Min
Max
Units
DCM_RST_PW_MIN
Minimum duration of a RST pulse width
3
–
CLKIN cycles
Notes:
1.
This limit only applies to applications that use the DCM DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV). The DCM
DFS outputs (CLKFX, CLKFXDV, CLKFX180) are unaffected.
Table 61: Frequency Synthesis
Attribute
Min
Max
CLKFX_MULTIPLY (DCM_SP)
2
32
CLKFX_DIVIDE (DCM_SP)
1
32
CLKDV_DIVIDE (DCM_SP)
1.5
16
CLKFX_MULTIPLY (DCM_CLKGEN)
2
256
CLKFX_DIVIDE (DCM_CLKGEN)
1
256
CLKFXDV_DIVIDE (DCM_CLKGEN)
2
32
Table 62: DCM Switching Characteristics
Symbol
Description
Speed Grade
Units
-3
-3N
-2
-1L
TDMCCK_PSEN/ TDMCKC_PSEN
PSEN Setup/Hold
1.50/
0.00
1.50/
0.00
1.50/
0.00
1.50/
0.00
ns
TDMCCK_PSINCDEC/ TDMCKC_PSINCDEC
PSINCDEC Setup/Hold
1.50/
0.00
1.50/
0.00
1.50/
0.00
1.50/
0.00
ns
TDMCKO_PSDONE
Clock to out of PSDONE
1.50
ns
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