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參數(shù)資料
型號(hào): XC5VLX50-1FF324I
廠商: Xilinx Inc
文件頁(yè)數(shù): 20/91頁(yè)
文件大小: 0K
描述: IC FPGA VIRTEX-5 50K 324FBGA
標(biāo)準(zhǔn)包裝: 1
系列: Virtex®-5 LX
LAB/CLB數(shù): 3600
邏輯元件/單元數(shù): 46080
RAM 位總計(jì): 1769472
輸入/輸出數(shù): 220
電源電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
工作溫度: -40°C ~ 100°C
封裝/外殼: 324-BBGA,F(xiàn)CBGA
供應(yīng)商設(shè)備封裝: 324-FCBGA(19x19)
配用: 568-5088-ND - BOARD DEMO DAC1408D750
HW-V5-ML561-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML550-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-V5-ML521-UNI-G-ND - EVALUATION PLATFORM VIRTEX-5
HW-AFX-FF324-500-G-ND - BOARD DEV VIRTEX 5 FF324
HW-V5GBE-DK-UNI-G-ND - KIT DEV V5 LXT GIGABIT ETHERNET
122-1508-ND - EVALUATION PLATFORM VIRTEX-5
Virtex-5 FPGA Data Sheet: DC and Switching Characteristics
DS202 (v5.3) May 5, 2010
Product Specification
27
External Reference Inputs(4)
Positive Reference Input
Voltage Range
VREFP
Measured Relative to VREFN
2.45
2.5
2.55
Volts
Negative Reference Input
Voltage Range
VREFN
Measured Relative to AGND
–50
0
100
mV
Input current
IREF
ADCCLK
= 5.2 MHz
100
A
Power Requirements
Analog Power Supply
AVDD
Measured Relative to AVSS
2.45
2.5
2.55
Volts
Analog Supply Current
AIDD
ADCCLK
= 5.2 MHz
5
13
mA
Notes:
1.
Offset and gain errors are removed by enabling the System Monitor automatic gain calibration feature. See UG192: Virtex-5 FPGA System
Monitor User Guide.
2.
See "System Monitor Timing" in UG192: Virtex-5 FPGA System Monitor User Guide.
3.
See "Analog Inputs" in UG192: Virtex-5 FPGA System Monitor User Guide for a detailed description.
4.
Any variation in the reference voltage from the nominal VREFP = 2.5V and VREFN = 0V will result is a deviation from the ideal transfer
function.This also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). However, for external
ratiometric type applications allowing the supply voltage and reference to vary by ±2% is permitted.
Table 51: Analog-to-Digital Specifications (Cont’d)
Parameter
Symbol
Comments/Conditions
Min
Typ
Max
Units
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