參數(shù)資料
型號(hào)： XC4VFX12-10SF363I
廠商： Xilinx Inc
文件頁(yè)數(shù)： 37/58頁(yè)
文件大?。?/td> 0K
描述： IC FPGA VIRTEX-4FX 363FCBGA
標(biāo)準(zhǔn)包裝： 90
系列： Virtex®-4 FX
LAB/CLB數(shù)： 1368
邏輯元件/單元數(shù)： 12312
RAM 位總計(jì)： 663552
輸入/輸出數(shù)： 240
電源電壓： 1.14 V ~ 1.26 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 363-FBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 363-FCBGA（17x17）
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
42
Table 50: Miscellaneous Timing Parameters
Symbol
Description
Speed Grade
Units
-12
-11
-10
Time Required to Achieve LOCK
T_LOCK_DLL_240
DLL output – Frequency range > 240 MHz (2)
20
s
T_LOCK_DLL_120_240
DLL output – Frequency range 120 - 240 MHz (1,2)
63
s
T_LOCK_DLL_60_120
DLL output – Frequency range 60 - 120 MHz (1,2)
225
s
T_LOCK_DLL_50_60
DLL output – Frequency range 50 - 60 MHz(1,2)
325
s
T_LOCK_DLL_40_50
DLL output – Frequency range 40 - 50 MHz (1,2)
500
s
T_LOCK_DLL_30_40
DLL output – Frequency range 30 - 40 MHz (1,2)
900
s
T_LOCK_DLL_24_30
DLL output – Frequency range 24 - 30 MHz(1,2)
1250
s
T_LOCK_DLL_30
DLL output – Frequency range < 30 MHz (2)
1250
s
T_LOCK_FX_MAX
DFS outputs(3)
10
ms
T_LOCK_DLL_FINE_SHIFT
Multiplication factor for DLL lock time with Fine Shift
2
Fine Phase Shifting
FINE_SHIFT_RANGE_MS
Absolute shifting range in maximum speed mode
7
ns
FINE_SHIFT_RANGE_MR
Absolute shifting range in maximum range mode
10
ns
Delay Lines
DCM_TAP_MS_MIN
Tap delay resolution (Min) in maximum speed mode
5
ps
DCM_TAP_MS_MAX
Tap delay resolution (Max) in maximum speed mode
40
ps
DCM_TAP_MR_MIN
Tap delay resolution (Min) in maximum range mode
10
ps
DCM_TAP_MR_MAX
Tap delay resolution (Max) in maximum range mode
60
ps
Input Signal Requirements
DCM_RESET(4)
Minimum duration that RST must be held asserted
200
ms
Maximum duration that RST can be held asserted(5)
10
sec
DCM_INPUT_CLOCK_STOP
Maximum duration that CLKIN and CLKFB can be
stopped(6,7)
100
ms
Notes:
1.
For boundary frequencies, choose the higher delay.
2.
DLL Outputs are used in these instances to describe the outputs: CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, and CLKDV.
3.
DFS Outputs are used in these instances to describe the outputs: CLKFX and CLKFX180.
4.
CLKIN must be present and stable during the DCM_RESET.
5.
This only applies to production step 1 LX and SX devices. For these devices, use the design solutions described in Answer Record 21127 for support
of longer reset durations. Production step 2 LX and SX devices and all production FX devices do not have this requirement.
6.
For production step 1 LX and SX devices, use the design solutions described in Answer Record 21127 for support of longer durations of stopped
clocks. For production step 2 LX and SX devices and all production FX devices, the ISE software automatically inserts a small macro to support
longer durations of stopped clocks.
7.
For all stepping levels, once the input clock is toggling again and stable after being stopped, DCM must be reset.
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