參數(shù)資料
型號： XC4VFX100-11FFG1517I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 10544 CLBS, 1181 MHz, PBGA1517
封裝： LEAD FREE, FBGA-1517
文件頁數(shù)： 9/58頁
文件大?。?/td> 1863K
代理商： XC4VFX100-11FFG1517I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
17
Table 25: RocketIO Receiver Switching Characteristics
Description
Symbol
Conditions
Min
Typ
Max
Units
Serial data rate, -10
FGRX
0.622
3.125
Gb/s
Serial data rate, -11
FGRX
0.622
6.5
Gb/s
XAUI Receive Jitter Tolerance (8B/10B CJPAT) (2)
Rate (Gb/s) Mode(3)
Frequency
Receive Deterministic Jitter Tolerance
TDJTOL
3.125
ACDR
0.37
UI(1)
Receive Total Jitter Tolerance
TTJTOL(6)
3.125
ACDR
0.65
Receive Sinusoidal Jitter Tolerance
TSJTOL(7)
3.125
ACDR
f = 22.1 kHz
8.5
3.125
ACDR
f = 1.875 MHz
0.10
3.125
ACDR
f = 20 MHz
0.10
General Receive Jitter Tolerance
Rate (Gb/s)
Pattern
Receive deterministic jitter tolerance
TDJTOL(2,4)
6.5(5)
ACDR
PRBS7
0.65
UI(1)
5.0(5)
ACDR
PRBS7
0.65
4.25(5)
ACDR
PRBS7
0.65
3.125
ACDR
PRBS7
0.60
2.5
ACDR
PRBS7
0.55
1.25
ACDR
PRBS7
0.50
1.25
DCDR
PRBS7
0.50
1.25
DCDR
PRBS31
0.40
0.622
DCDR
PRBS31
0.40
Sinusoidal jitter tolerance
TSJTOL
6.5(9)
ACDR
PRBS7
0.65
5.0(9)
ACDR
PRBS7
0.65
4.25(9)
ACDR
PRBS7
0.65
3.125(8)
ACDR
PRBS7
0.50
2.5(8)
ACDR
PRBS7
0.50
1.25(8)
ACDR
PRBS7
0.50
1.25(8)
DCDR
PRBS7
0.55
1.25(8)
DCDR
PRBS31
0.35
DCDR
PRBS31
0.55
RXUSRCLK frequency
TRX
For slower speed grades = MaxDataRate/32
250
MHz
RXUSRCLK2 frequency
TRX2
250
MHz
RXUSRCLK duty cycle
TRXDC
40
60
%
RXUSRCLK2 duty cycle
TRX2DC
40
60
%
Differential input skew
TISKEW
20
ps
Differential receive input sensitivity(2)
VEYE
110
mV
On-chip AC coupling corner frequency
Signal detect response time
RXSIGDETResponsetime
30
ns
Input capacitance at the Die
CDIE
fF
Excess capacitance at the solder ball
CBALL
fF
Notes:
1.
UI = Unit Interval
2.
Using receiver equalization setting of 111 (14 dB).
3.
ACDR = Analog CDR and DCDR = Digital CDR.
4.
Deterministic jitter (DJ) is composed of 75% ISI + 25% high frequency
sinusoidal jitter (SJ).
5.
Deterministic Jitter (DJ) composed of ISI + 0.10 UI of high frequency SJ +
0.15 UI of RJ.
6.
Sum of DJ, random jitter (RJ) of at least 0.55 UI, and sinusoidal jitter
as defined by mask in IEEE Std 802.3ae-2002, Figure 47-5.
7.
SJ in addition to 0.55 UI of DJ +RJ.
8.
Jitter frequency = 5 MHz.
9.
Jitter frequency = 10 MHz.
相關(guān)PDF資料
PDF描述
XC4VFX100-12FFG1152C FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-12FFG1517C FPGA, 10544 CLBS, 1181 MHz, PBGA1517
XC5206-3PCG84I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQCC84
XC5206-3PQG100I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQFP100
XC5206-3PQG160I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQFP160
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XC4VFX100-12FF1152C 制造商:Xilinx 功能描述:
XC4VFX100-12FF1517C 制造商:Xilinx 功能描述:
XC4VFX100-12FFG1152C 功能描述:IC FPGA VIRTEX-4FX 100K 1152FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
XC4VFX100-12FFG1152CES 制造商:Xilinx 功能描述:
XC4VFX100-12FFG1517C 功能描述:IC FPGA VIRTEX-4FX 100K 1517FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產(chǎn)品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應(yīng)商設(shè)備封裝:120-CPGA（34.55x34.55）
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*