參數(shù)資料
型號： XC4VFX100-11FFG1517I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 10544 CLBS, 1181 MHz, PBGA1517
封裝： LEAD FREE, FBGA-1517
文件頁數(shù)： 16/58頁
文件大?。?/td> 1863K
代理商： XC4VFX100-11FFG1517I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
23
I/O Standard Adjustment Measurement Methodology
Input Delay Measurements
Table 30 shows the test setup parameters used for measuring input delay.
Table 30: Input Delay Measurement Methodology
Description
I
/O Standard
Attribute
VL(1,2)
VH(1,2)
VMEAS
(1,4,5)
VREF
(1,3,5)
LVTTL (Low-Voltage Transistor-Transistor Logic)
LVTTL
0
3.0
1.4
–
LVCMOS (Low-Voltage CMOS), 3.3V
LVCMOS33
0
3.3
1.65
–
LVCMOS, 2.5V
LVCMOS25
0
2.5
1.25
–
LVCMOS, 1.8V
LVCMOS18
0
1.8
0.9
–
LVCMOS, 1.5V
LVCMOS15
0
1.5
0.75
–
PCI (Peripheral Component Interface),
33 MHz, 3.3V
PCI33_3
Per PCI Specification
–
PCI, 66 MHz, 3.3V
PCI66_3
Per PCI Specification
–
PCI-X, 133 MHz, 3.3V
PCIX
Per PCI-X Specification
–
GTL (Gunning Transceiver Logic)
GTL
VREF –0.2
VREF +0.2
VREF
0.80
GTL Plus
GTLP
VREF –0.2
VREF +0.2
VREF
1.0
HSTL (High-Speed Transceiver Logic),
Class I & II
HSTL_I, HSTL_II
VREF –0.5
VREF +0.5
VREF
0.75
HSTL, Class III & IV
HSTL_III, HSTL_IV
VREF –0.5
VREF +0.5
VREF
0.90
HSTL, Class I & II, 1.8V
HSTL_I_18, HSTL_II_18
VREF –0.5
VREF +0.5
VREF
0.90
HSTL, Class III & IV, 1.8V
HSTL_III_18,
HSTL_IV_18
VREF –0.5
VREF +0.5
VREF
1.08
SSTL (Stub Terminated Transceiver Logic),
Class I & II, 3.3V
SSTL3_I, SSTL3_II
VREF –1.00
VREF +1.00
VREF
1.5
SSTL, Class I & II, 2.5V
SSTL2_I, SSTL2_II
VREF –0.75
VREF +0.75
VREF
1.25
SSTL, Class I & II, 1.8V
SSTL18_I, SSTL18_II
VREF –0.5
VREF +0.5
VREF
0.90
AGP-2X/AGP (Accelerated Graphics Port)
AGP
VREF –
(0.2 xVCCO)
VREF +
(0.2 xVCCO)
VREF
AGP
Spec
LVDS (Low-Voltage Differential Signaling), 2.5V
LVDS_25
1.2 – 0.125
1.2 + 0.125
1.2
LVDSEXT (LVDS Extended Mode), 2.5V
LVDSEXT_25
1.2 – 0.125
1.2 + 0.125
1.2
ULVDS (Ultra LVDS), 2.5V
ULVDS_25
0.6 – 0.125
0.6 + 0.125
0.6
LDT (HyperTransport), 2.5V
LDT_25
0.6 – 0.125
0.6 + 0.125
0.6
Notes:
1.
Input delay measurement methodology parameters for LVDCI and HSLVDCI are the same as for LVCMOS standards of the same voltage.
Parameters for all other DCI standards are the same as for the corresponding non-DCI standards.
2.
Input waveform switches between VLand VH.
3.
Measurements are made at typical, minimum, and maximum VREF values. Reported delays reflect worst case of these measurements. VREF values
listed are typical.
4.
Input voltage level from which measurement starts.
5.
This is an input voltage reference that bears no relation to the VREF / VMEAS parameters found in IBIS models and/or noted in Figure 4.
相關PDF資料
PDF描述
XC4VFX100-12FFG1152C FPGA, 10544 CLBS, 1181 MHz, PBGA1152
XC4VFX100-12FFG1517C FPGA, 10544 CLBS, 1181 MHz, PBGA1517
XC5206-3PCG84I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQCC84
XC5206-3PQG100I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQFP100
XC5206-3PQG160I FPGA, 196 CLBS, 6000 GATES, 83 MHz, PQFP160
相關代理商/技術參數(shù)
參數(shù)描述
XC4VFX100-12FF1152C 制造商:Xilinx 功能描述:
XC4VFX100-12FF1517C 制造商:Xilinx 功能描述:
XC4VFX100-12FFG1152C 功能描述:IC FPGA VIRTEX-4FX 100K 1152FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
XC4VFX100-12FFG1152CES 制造商:Xilinx 功能描述:
XC4VFX100-12FFG1517C 功能描述:IC FPGA VIRTEX-4FX 100K 1517FBGA RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:Virtex®-4 FX 產品變化通告:XC4000(E,L) Discontinuation 01/April/2002 標準包裝:24 系列:XC4000E/X LAB/CLB數(shù):100 邏輯元件/單元數(shù):238 RAM 位總計:3200 輸入/輸出數(shù):80 門數(shù):3000 電源電壓:4.5 V ~ 5.5 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 100°C 封裝/外殼:120-BCBGA 供應商設備封裝:120-CPGA（34.55x34.55）
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*