參數(shù)資料
型號： XC4VFX100-10FFG1152I
廠商： XILINX INC
元件分類： FPGA
英文描述： FPGA, 10544 CLBS, 1028 MHz, PBGA1152
封裝： LEAD FREE, FBGA-1152
文件頁數(shù)： 27/58頁
文件大?。?/td> 1863K
代理商： XC4VFX100-10FFG1152I
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
DS302 (v3.7) September 9, 2009
Product Specification
33
Block RAM and FIFO Switching Characteristics
Table 40: Block RAM Switching Characteristics
Symbol
Description
Speed Grade
Units
-12
-11
-10
Sequential Delays
TRCKO_DORA
Clock CLK to DOUT output (without output register)(2)
1.65
1.83
2.10
ns, Max
Clock CLK to DOUT output with ECC
(without output register)
3.00
3.33
3.83
ns, Max
TRCKO_DOA
Clock CLK to DOUT output (with output register)(3)
0.72
0.80
0.92
ns, Max
Clock CLK to DOUT output with ECC (with output
register)
2.00
2.20
2.50
ns, Max
Setup and Hold Times Before Clock CLK
TRCCK_ADDR / TRCKC_ADDR
ADDR inputs
0.34
0.26
0.37
0.28
0.43
0.33
ns, Min
TRDCK_DI / TRCKD_DI
DIN inputs(4)
0.18
0.26
0.20
0.28
0.23
0.33
ns, Min
TRCCK_EN / TRCKC_EN
EN input(5)
0.41
0.26
0.45
0.28
0.52
0.33
ns, Min
TRCCK_REGCE /TRCKC_REGCE
CE input of output register
0.25
0.26
0.27
0.28
0.32
0.33
ns, Min
TRCCK_SSR / TRCKC_SSR
RST input
0.25
0.26
0.27
0.28
0.32
0.33
ns, Min
TRCCK_WE / TRCKC_WE
WEN input
0.59
0.26
0.65
0.28
0.75
0.33
ns, Min
Maximum Frequency
FMAX
Write first and no change mode
500.00
450.45
400.00
MHz
FMAX
Read first mode
500.00
450.45
400.00
MHz
CLK-to-CLK
Read first mode
500.00
450.45
400.00
MHz
Notes:
1.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
2.
TRCKO_DORA includes TRCKO_DOWA, TRCKO_DOPAR, and TRCKO_DOPAW as well as the B port equivalent timing parameters.
3.
TRCKO_DOA includes TRCKO_DOPA as well as the B port equivalent timing parameters.
4.
TRCKO_DI includes both A and B inputs as well as the parity inputs of A and B.
5.
Xilinx block RAMs do not have asynchronous inputs on an enabled port address. During the time that a port is enabled, its addresses must be stable
during the specified set-up time. Do not create an asynchronous input on an enabled port address.
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