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參數(shù)資料
| 型號： | XC4036XLA-09HQ240C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC FPGA C 2.5V 288 I/O 240HQFP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | XC4000XLA/XV |
| LAB/CLB數(shù)： | 1296 |
| 邏輯元件/單元數(shù)： | 3078 |
| RAM 位總計： | 41472 |
| 輸入/輸出數(shù)： | 193 |
| 門數(shù)： | 36000 |
| 電源電壓： | 3 V ~ 3.6 V |
| 安裝類型： | 表面貼裝 |
| 工作溫度： | 0°C ~ 85°C |
| 封裝/外殼： | 240-BFQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 240-PQFP（32x32） |
| 其它名稱： | 155001A Q1155001A XC4036XLA09HQ240C |
R
DS015 (v2.0) March 1, 2013 - Product Specification
6-163
XC4000XLA/XV Field Programmable Gate Arrays
6
Product Obsolete/Under Obsolescence
I/O Signalling Standards
XLA and XV devices are compatible with TTL, LVTTL, PCI
3V, PCI 5V and LVCMOS signalling. The various standards
are illustrated in Table 6 and the signaling environment is
illustrated in Figure 4.
VCC Clamping
XLA/XV devices are fully 5V TTL I/O compatible if VCC
clamping is not enabled. The I/O pins can withstand input
voltages up to 7V. With VCC clamping enabled, the XLA/XV
devices will begin to clamp input voltages to one diode volt-
age drop above VCC. In both cases negative voltage is
clamped to one diode voltage drop below ground.
XLA/XV devices maintain LVTTL I/O compatibility when
VCC clamping is enabled, however full 5.0V TTL I/O com-
patibility is sacrificed.
Overshoot and Undershoot
Ringing wave forms are allowed on XLA/XV inputs as long
as undershoot is limited to -2.0V and overshoot is limited to
+7.0V and current is limited to 100 mA for less than 10 ns.
If VCC clamping is enabled then overshoot will begin to be
clamped at VCC/VCCIO plus one diode voltage drop and
undershoot will be clamped to ground minus one diode volt-
age drop. In either case the current must be limited to 100
mA per pin for less than 10 ns.
Express Configuration Mode
Express configuration mode is similar to Slave Serial con-
figuration mode, except that data is processed one byte per
CCLK cycle instead of one bit per CCLK cycle. An external
source is used to drive CCLK, while byte-wide data is
loaded directly into the configuration data shift registers
(Figure 5). A CCLK frequency of 10 MHz is equivalent to a
80 MHz serial rate, because eight bits of configuration data
are loaded per CCLK cycle. Express mode does not sup-
port CRC error checking, but does support constant-field
error checking. A length count is not used in Express mode.
Express mode must be specified as an option to the BitGen
program, which generates the bitstream. The Express
mode bitstream is not compatible with the other configura-
tion modes. Express mode is selected by a <010> on the
mode pins (M2, M1, M0).
The first byte of parallel configuration data must be avail-
able at the D inputs of the FPGA a short setup time before
the second rising CCLK edge. Subsequent data bytes are
clocked in on each consecutive rising CCLK edge
Table 6: I/O Standards supported by XC4000XLA and XV FPGAs
Signaling
Standard
VCC
Clamping
Output Drive
VIH_MAX
VIH MIN
VIL MAX
VOH MIN
VOL MAX
TTL
Not allowed
12/24 mA
5.5
2.0
0.8
2.4
0.4
LVTTL
OK
12/24 mA
3.6
2.0
0.8
2.4
0.4
PCI5V
Not allowed
24 mA
5.5
2.0
0.8
2.4
0.4
PCI3V
Required
12 mA
3.6
50% of
VCC/VCCIO
30% of
VCC/VCCIO
90% of
VCC/VCCIO
10% of
VCC/VCCIO
LVCMOS 3V
OK
12/24 mA
3.6
50% of
VCC/VCCIO
30% of
VCC/VCCIO
90% of
VCC/VCCIO
10% of
VCC/VCCIO
VCC (5 V)
5.0 V Power
3.3 V Power
2.5 V Power
Ground
TTL
LVTTL
5 Volt Device
VCCIO VCCINT
LVTTL
XC4000XV
VCC (3.3 V)
3.3 Volt Device
X7147
Figure 4: The Signalling Environment for XLA/XV FPGAs. For XLA devices the VCCIO and VCCINT supplies are
replaced by a single 3.3 Volt VCC supply, however, all indicated I/O signalling is still supported.
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