參數(shù)資料
型號： XC4028XL-3HQ240I
廠商： Xilinx Inc
文件頁數(shù)： 46/68頁
文件大?。?/td> 0K
描述： IC FPGA I-TEMP 3.3V 3SPD 240HQFP
產(chǎn)品變化通告： Product Discontinuation 27/Apr/2010
標(biāo)準(zhǔn)包裝： 1
系列： XC4000E/X
LAB/CLB數(shù)： 1024
邏輯元件/單元數(shù)： 2432
RAM 位總計(jì)： 32768
輸入/輸出數(shù)： 193
門數(shù)： 28000
電源電壓： 3 V ~ 3.6 V
安裝類型： 表面貼裝
工作溫度： -40°C ~ 100°C
封裝/外殼： 240-BFQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 240-PQFP（32x32）
R
XC4000E and XC4000X Series Field Programmable Gate Arrays
6-54
May 14, 1999 (Version 1.6)
Start-up from a User Clock (STARTUP.CLK)
When, instead of CCLK, a user-supplied start-up clock is
selected, Q1 is used to bridge the unknown phase relation-
ship between CCLK and the user clock. This arbitration
causes an unavoidable one-cycle uncertainty in the timing
of the rest of the start-up sequence.
DONE Goes High to Signal End of Conguration
XC4000 Series devices read the expected length count
from the bitstream and store it in an internal register. The
length count varies according to the number of devices and
the composition of the daisy chain. Each device also counts
the number of CCLKs during conguration.
Two conditions have to be met in order for the DONE pin to
go high:
the chip's internal memory must be full, and
the conguration length count must be met,
exactly.
This is important because the counter that determines
when the length count is met begins with the very rst
CCLK, not the rst one after the preamble.
Therefore, if a stray bit is inserted before the preamble, or
the data source is not ready at the time of the rst CCLK,
the internal counter that holds the number of CCLKs will be
one ahead of the actual number of data bits read. At the
end of conguration, the conguration memory will be full,
but the number of bits in the internal counter will not match
the expected length count.
As a consequence, a Master mode device will continue to
send out CCLKs until the internal counter turns over to
zero, and then reaches the correct length count a second
time. This will take several seconds [224
CCLK period] —
which is sometimes interpreted as the device not congur-
ing at all.
If it is not possible to have the data ready at the time of the
rst CCLK, the problem can be avoided by increasing the
number in the length count by the appropriate value. The
XACT User Guide includes detailed information about man-
ually altering the length count.
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by the bitstream generation software.
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 50 k
- 100 k pull-up. The delay from
DONE High to active user I/O is controlled by an option to
the bitstream generation software.
Release of Global Set/Reset After DONE Goes
High
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all ip-ops are held
in their initial set or reset state. The delay from DONE High
to GSR inactive is controlled by an option to the bitstream
generation software.
Conguration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in Figure 47 on page 53. If CCLK is
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
Conguration Through the Boundary Scan
Pins
XC4000 Series devices can be congured through the
boundary scan pins. The basic procedure is as follows:
Power up the FPGA with INIT held Low (or drive the
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after conguration if
a resistor is used to hold INIT Low.
Issue the CONFIG command to the TMS input
Wait for INIT to go High
Sequence the boundary scan Test Access Port to the
SHIFT-DR state
Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note XAPP017, “
Boundary Scan in XC4000 Devices.” This
application note also applies to XC4000E and XC4000X
devices.
Product Obsolete or Under Obsolescence
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